diff options
| -rw-r--r-- | Makefile | 9 | ||||
| -rw-r--r-- | inst.chisel | 184 | ||||
| -rw-r--r-- | instr-table.tex | 1711 | ||||
| -rw-r--r-- | opcodes | 367 | ||||
| -rw-r--r-- | opcodes-custom | 48 | ||||
| -rwxr-xr-x | parse-opcodes | 429 |
6 files changed, 1477 insertions, 1271 deletions
@@ -3,7 +3,7 @@ PK_H := ../riscv-pk/pk/riscv-opc.h GAS_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h XCC_H := ../riscv-gcc/gcc-4.6.1/gcc/config/riscv/riscv-opc.h -install: $(ISASIM_H) $(PK_H) $(GAS_H) $(XCC_H) inst.v instr-table.tex +install: $(ISASIM_H) $(PK_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex $(ISASIM_H): opcodes parse-opcodes ./parse-opcodes -isasim < $< > $@ @@ -13,15 +13,16 @@ $(PK_H): opcodes parse-opcodes $(GAS_H): opcodes opcodes-hwacha opcodes-rvc opcodes-custom parse-opcodes ./parse-opcodes -disasm < $< > $@ - ./parse-opcodes -disasm < opcodes-hwacha >> $@ + #./parse-opcodes -disasm < opcodes-hwacha >> $@ ./parse-opcodes -disasm < opcodes-rvc >> $@ ./parse-opcodes -disasm < opcodes-custom >> $@ $(XCC_H): opcodes parse-opcodes ./parse-opcodes -disasm < $< > $@ -inst.v: opcodes parse-opcodes - ./parse-opcodes -verilog < $< > $@ +inst.chisel: opcodes parse-opcodes + ./parse-opcodes -chisel < $< > $@ + ./parse-opcodes -chisel < opcodes-custom >> $@ instr-table.tex: opcodes parse-opcodes ./parse-opcodes -tex < $< > $@ diff --git a/inst.chisel b/inst.chisel new file mode 100644 index 0000000..b77863a --- /dev/null +++ b/inst.chisel @@ -0,0 +1,184 @@ + /* Automatically generated by parse-opcodes */ + def JAL = Bits("b?????????????????????????1100111") + def JALR = Bits("b?????????????????000?????1101111") + def BEQ = Bits("b?????????????????000?????1100011") + def BNE = Bits("b?????????????????001?????1100011") + def BLT = Bits("b?????????????????100?????1100011") + def BGE = Bits("b?????????????????101?????1100011") + def BLTU = Bits("b?????????????????110?????1100011") + def BGEU = Bits("b?????????????????111?????1100011") + def LUI = Bits("b?????????????????????????0110111") + def AUIPC = Bits("b?????????????????????????0010111") + def ADDI = Bits("b?????????????????000?????0010011") + def SLLI = Bits("b010000???????????001?????0010011") + def SLTI = Bits("b?????????????????010?????0010011") + def SLTIU = Bits("b?????????????????011?????0010011") + def XORI = Bits("b?????????????????100?????0010011") + def SRLI = Bits("b000000???????????101?????0010011") + def SRAI = Bits("b010000???????????101?????0010011") + def ORI = Bits("b?????????????????110?????0010011") + def ANDI = Bits("b?????????????????111?????0010011") + def ADD = Bits("b0000000??????????000?????0110011") + def SUB = Bits("b0100000??????????000?????0110011") + def SLL = Bits("b0000000??????????001?????0110011") + def SLT = Bits("b0000000??????????010?????0110011") + def SLTU = Bits("b0000000??????????011?????0110011") + def XOR = Bits("b0000000??????????100?????0110011") + def SRL = Bits("b0000000??????????101?????0110011") + def SRA = Bits("b0100000??????????101?????0110011") + def OR = Bits("b0000000??????????110?????0110011") + def AND = Bits("b0000000??????????111?????0110011") + def MUL = Bits("b0000001??????????000?????0110011") + def MULH = Bits("b0000001??????????001?????0110011") + def MULHSU = Bits("b0000001??????????010?????0110011") + def MULHU = Bits("b0000001??????????011?????0110011") + def DIV = Bits("b0000001??????????100?????0110011") + def DIVU = Bits("b0000001??????????101?????0110011") + def REM = Bits("b0000001??????????110?????0110011") + def REMU = Bits("b0000001??????????111?????0110011") + def ADDIW = Bits("b?????????????????000?????0011011") + def SLLIW = Bits("b0100000??????????001?????0011011") + def SRLIW = Bits("b0000000??????????101?????0011011") + def SRAIW = Bits("b0100000??????????101?????0011011") + def ADDW = Bits("b0000000??????????000?????0111011") + def SUBW = Bits("b0100000??????????000?????0111011") + def SLLW = Bits("b0000000??????????001?????0111011") + def SRLW = Bits("b0000000??????????101?????0111011") + def SRAW = Bits("b0100000??????????101?????0111011") + def MULW = Bits("b0000001??????????000?????0111011") + def DIVW = Bits("b0000001??????????100?????0111011") + def DIVUW = Bits("b0000001??????????101?????0111011") + def REMW = Bits("b0000001??????????110?????0111011") + def REMUW = Bits("b0000001??????????111?????0111011") + def LB = Bits("b?????????????????000?????0000011") + def LH = Bits("b?????????????????001?????0000011") + def LW = Bits("b?????????????????010?????0000011") + def LD = Bits("b?????????????????011?????0000011") + def LBU = Bits("b?????????????????100?????0000011") + def LHU = Bits("b?????????????????101?????0000011") + def LWU = Bits("b?????????????????110?????0000011") + def SB = Bits("b?????????????????000?????0100011") + def SH = Bits("b?????????????????001?????0100011") + def SW = Bits("b?????????????????010?????0100011") + def SD = Bits("b?????????????????011?????0100011") + def AMOADD_W = Bits("b00000????????????010?????0101111") + def AMOXOR_W = Bits("b00100????????????010?????0101111") + def AMOOR_W = Bits("b01000????????????010?????0101111") + def AMOAND_W = Bits("b01100????????????010?????0101111") + def AMOMIN_W = Bits("b10000????????????010?????0101111") + def AMOMAX_W = Bits("b10100????????????010?????0101111") + def AMOMINU_W = Bits("b11000????????????010?????0101111") + def AMOMAXU_W = Bits("b11100????????????010?????0101111") + def AMOSWAP_W = Bits("b00001????????????010?????0101111") + def LR_W = Bits("b00010??00000?????010?????0101111") + def SC_W = Bits("b00011????????????010?????0101111") + def AMOADD_D = Bits("b00000????????????011?????0101111") + def AMOXOR_D = Bits("b00100????????????011?????0101111") + def AMOOR_D = Bits("b01000????????????011?????0101111") + def AMOAND_D = Bits("b01100????????????011?????0101111") + def AMOMIN_D = Bits("b10000????????????011?????0101111") + def AMOMAX_D = Bits("b10100????????????011?????0101111") + def AMOMINU_D = Bits("b11000????????????011?????0101111") + def AMOMAXU_D = Bits("b11100????????????011?????0101111") + def AMOSWAP_D = Bits("b00001????????????011?????0101111") + def LR_D = Bits("b00010??00000?????011?????0101111") + def SC_D = Bits("b00011????????????011?????0101111") + def FENCE = Bits("b?????????????????000?????0001111") + def FENCE_I = Bits("b?????????????????001?????0001111") + def SYSCALL = Bits("b00000000000000000000000001110111") + def BREAK = Bits("b00000000000000000001000001110111") + def RDCYCLE = Bits("b00000000000000000100?????1110111") + def RDTIME = Bits("b00000010000000000100?????1110111") + def RDINSTRET = Bits("b00000100000000000100?????1110111") + def MTPCR = Bits("b0000000??????????000?????1110011") + def MFPCR = Bits("b000000000000?????001?????1110011") + def SETPCR = Bits("b?????????????????010?????1110011") + def CLEARPCR = Bits("b?????????????????011?????1110011") + def ERET = Bits("b00000000000000000100000001110011") + def FADD_S = Bits("b0000000??????????????????1010011") + def FSUB_S = Bits("b0000100??????????????????1010011") + def FMUL_S = Bits("b0001000??????????????????1010011") + def FDIV_S = Bits("b0001100??????????????????1010011") + def FSQRT_S = Bits("b001000000000?????????????1010011") + def FSGNJ_S = Bits("b0010100??????????000?????1010011") + def FSGNJN_S = Bits("b0011000??????????000?????1010011") + def FSGNJX_S = Bits("b0011100??????????000?????1010011") + def FADD_D = Bits("b0000001??????????????????1010011") + def FSUB_D = Bits("b0000101??????????????????1010011") + def FMUL_D = Bits("b0001001??????????????????1010011") + def FDIV_D = Bits("b0001101??????????????????1010011") + def FSQRT_D = Bits("b001000100000?????????????1010011") + def FSGNJ_D = Bits("b0010101??????????000?????1010011") + def FSGNJN_D = Bits("b0011001??????????000?????1010011") + def FSGNJX_D = Bits("b0011101??????????000?????1010011") + def FCVT_L_S = Bits("b010000000000?????????????1010011") + def FCVT_LU_S = Bits("b010010000000?????????????1010011") + def FCVT_W_S = Bits("b010100000000?????????????1010011") + def FCVT_WU_S = Bits("b010110000000?????????????1010011") + def FCVT_L_D = Bits("b010000100000?????????????1010011") + def FCVT_LU_D = Bits("b010010100000?????????????1010011") + def FCVT_W_D = Bits("b010100100000?????????????1010011") + def FCVT_WU_D = Bits("b010110100000?????????????1010011") + def FCVT_S_L = Bits("b011000000000?????????????1010011") + def FCVT_S_LU = Bits("b011010000000?????????????1010011") + def FCVT_S_W = Bits("b011100000000?????????????1010011") + def FCVT_S_WU = Bits("b011110000000?????????????1010011") + def FCVT_D_L = Bits("b011000100000?????????????1010011") + def FCVT_D_LU = Bits("b011010100000?????????????1010011") + def FCVT_D_W = Bits("b011100100000?????????????1010011") + def FCVT_D_WU = Bits("b011110100000?????????????1010011") + def FCVT_S_D = Bits("b100010000000?????????????1010011") + def FCVT_D_S = Bits("b100000100000?????????????1010011") + def FEQ_S = Bits("b1010100??????????000?????1010011") + def FLT_S = Bits("b1011000??????????000?????1010011") + def FLE_S = Bits("b1011100??????????000?????1010011") + def FEQ_D = Bits("b1010101??????????000?????1010011") + def FLT_D = Bits("b1011001??????????000?????1010011") + def FLE_D = Bits("b1011101??????????000?????1010011") + def FMIN_S = Bits("b1100000??????????000?????1010011") + def FMAX_S = Bits("b1100100??????????000?????1010011") + def FMIN_D = Bits("b1100001??????????000?????1010011") + def FMAX_D = Bits("b1100101??????????000?????1010011") + def FMV_X_S = Bits("b111000000000?????000?????1010011") + def FMV_X_D = Bits("b111000100000?????000?????1010011") + def FRSR = Bits("b11101000000000000000?????1010011") + def FMV_S_X = Bits("b111100000000?????000?????1010011") + def FMV_D_X = Bits("b111100100000?????000?????1010011") + def FSSR = Bits("b111110000000?????000?????1010011") + def FLW = Bits("b?????????????????010?????0000111") + def FLD = Bits("b?????????????????011?????0000111") + def FSW = Bits("b?????????????????010?????0100111") + def FSD = Bits("b?????????????????011?????0100111") + def FMADD_S = Bits("b?????00??????????????????1000011") + def FMSUB_S = Bits("b?????00??????????????????1000111") + def FNMSUB_S = Bits("b?????00??????????????????1001011") + def FNMADD_S = Bits("b?????00??????????????????1001111") + def FMADD_D = Bits("b?????01??????????????????1000011") + def FMSUB_D = Bits("b?????01??????????????????1000111") + def FNMSUB_D = Bits("b?????01??????????????????1001011") + def FNMADD_D = Bits("b?????01??????????????????1001111") + /* Automatically generated by parse-opcodes */ + def CUSTOM0 = Bits("b?????????????????000?????0001011") + def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011") + def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011") + def CUSTOM0_RD = Bits("b?????????????????100?????0001011") + def CUSTOM0_RD_RS1 = Bits("b?????????????????110?????0001011") + def CUSTOM0_RD_RS1_RS2 = Bits("b?????????????????111?????0001011") + def CUSTOM1 = Bits("b?????????????????000?????0101011") + def CUSTOM1_RS1 = Bits("b?????????????????010?????0101011") + def CUSTOM1_RS1_RS2 = Bits("b?????????????????011?????0101011") + def CUSTOM1_RD = Bits("b?????????????????100?????0101011") + def CUSTOM1_RD_RS1 = Bits("b?????????????????110?????0101011") + def CUSTOM1_RD_RS1_RS2 = Bits("b?????????????????111?????0101011") + def CUSTOM2 = Bits("b?????????????????000?????1011011") + def CUSTOM2_RS1 = Bits("b?????????????????010?????1011011") + def CUSTOM2_RS1_RS2 = Bits("b?????????????????011?????1011011") + def CUSTOM2_RD = Bits("b?????????????????100?????1011011") + def CUSTOM2_RD_RS1 = Bits("b?????????????????110?????1011011") + def CUSTOM2_RD_RS1_RS2 = Bits("b?????????????????111?????1011011") + def CUSTOM3 = Bits("b?????????????????000?????1111011") + def CUSTOM3_RS1 = Bits("b?????????????????010?????1111011") + def CUSTOM3_RS1_RS2 = Bits("b?????????????????011?????1111011") + def CUSTOM3_RD = Bits("b?????????????????100?????1111011") + def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") + def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") diff --git a/instr-table.tex b/instr-table.tex index 22e28d5..6a26f36 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -6,486 +6,495 @@ \begin{center} \begin{tabular}{rccccccccccl} & -\instbitrange{31}{27} & -\instbitrange{26}{22} & -\instbitrange{21}{17} & -\instbit{16} & - & -\instbitrange{}{12} & -\instbitrange{11}{10} & -\instbit{9} & -\instbitrange{}{7} & +\multicolumn{1}{l}{\instbit{31}} & +\multicolumn{1}{r}{\instbit{27}} & +\instbit{26} & +\instbit{25} & +\multicolumn{2}{c}{\instbitrange{24}{20}} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbitrange{11}{7} & \instbitrange{6}{0} \\ \cline{2-11} + + & -\multicolumn{9}{|c|}{jump target} & -\multicolumn{1}{c|}{opcode} & J-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{upper immediate} & -\multicolumn{1}{c|}{opcode} & U-type \\ +\multicolumn{4}{|c|}{funct7} & +\multicolumn{2}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{opcode} & R-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm[11:7]} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{opcode} & I-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{imm[11:7]} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & B-type \\ +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{opcode} & S-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{imm[12, 10:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{6}{c|}{funct10} & -\multicolumn{1}{c|}{opcode} & R-type \\ +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{imm[4:1, 11]} & +\multicolumn{1}{c|}{opcode} & SB-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{3}{c|}{funct5} & -\multicolumn{1}{c|}{opcode} & R4-type \\ +\multicolumn{8}{|c|}{imm[31:12]} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{opcode} & U-type \\ \cline{2-11} - + & -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf RV32I Instruction Subset} & \\ +\multicolumn{8}{|c|}{imm[20, 10:1, 11, 19:12]} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{opcode} & UJ-type \\ \cline{2-11} - + & -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{imm20} & -\multicolumn{1}{c|}{0110111} & LUI rd,imm20 \\ +\multicolumn{10}{c}{} & \\ +& +\multicolumn{10}{c}{\bf RV32I Base Instruction Set} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{imm20} & -\multicolumn{1}{c|}{0010111} & AUIPC rd,imm20 \\ +\multicolumn{8}{|c|}{imm[31:12]} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0110111} & LUI rd,imm \\ \cline{2-11} & -\multicolumn{9}{|c|}{imm25} & -\multicolumn{1}{c|}{1101011} & J imm25 \\ +\multicolumn{8}{|c|}{imm[31:12]} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010111} & AUIPC rd,imm \\ \cline{2-11} & -\multicolumn{9}{|c|}{imm25} & -\multicolumn{1}{c|}{1101111} & JAL imm25 \\ +\multicolumn{8}{|c|}{imm[20, 10:1, 11, 19:12]} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{1100111} & JAL rd,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{1100111} & JALR rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{1101111} & JALR rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[12, 10:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{1100011} & BEQ rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:1, 11]} & +\multicolumn{1}{c|}{1100011} & BEQ rs1,rs2,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[12, 10:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{1100011} & BNE rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:1, 11]} & +\multicolumn{1}{c|}{1100011} & BNE rs1,rs2,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[12, 10:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{1100011} & BLT rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:1, 11]} & +\multicolumn{1}{c|}{1100011} & BLT rs1,rs2,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[12, 10:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{1100011} & BGE rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:1, 11]} & +\multicolumn{1}{c|}{1100011} & BGE rs1,rs2,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[12, 10:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{110} & -\multicolumn{1}{c|}{1100011} & BLTU rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:1, 11]} & +\multicolumn{1}{c|}{1100011} & BLTU rs1,rs2,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[12, 10:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{111} & -\multicolumn{1}{c|}{1100011} & BGEU rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:1, 11]} & +\multicolumn{1}{c|}{1100011} & BGEU rs1,rs2,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0000011} & LB rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000011} & LB rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0000011} & LH rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000011} & LH rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0000011} & LW rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000011} & LW rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{0000011} & LBU rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000011} & LBU rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0000011} & LHU rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000011} & LHU rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0100011} & SB rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{0100011} & SB rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0100011} & SH rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{0100011} & SH rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0100011} & SW rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{0100011} & SW rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0010011} & ADDI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & ADDI rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000000} & -\multicolumn{3}{c|}{shamt} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0010011} & SLLI rd,rs1,shamt \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & SLTI rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0010011} & SLTI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & SLTIU rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0010011} & SLTIU rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & XORI rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{0010011} & XORI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & ORI rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000000} & -\multicolumn{3}{c|}{shamt} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0010011} & SRLI rd,rs1,shamt \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & ANDI rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000001} & +\multicolumn{3}{|c|}{010000} & \multicolumn{3}{c|}{shamt} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0010011} & SRAI rd,rs1,shamt \\ +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & SLLI rd,rs1,shamt \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{3}{|c|}{000000} & +\multicolumn{3}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{110} & -\multicolumn{1}{c|}{0010011} & ORI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & SRLI rd,rs1,shamt \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{3}{|c|}{010000} & +\multicolumn{3}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{111} & -\multicolumn{1}{c|}{0010011} & ANDI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0010011} & SRAI rd,rs1,shamt \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & ADD rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & SUB rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & SLL rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{010} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & SLT rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{011} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & SLTU rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{100} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & XOR rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{101} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & SRL rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{101} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & SRA rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{110} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & OR rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{111} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & AND rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{00000} & +\multicolumn{1}{|c|}{0000} & +\multicolumn{4}{c|}{~~~pred~~~~} & +\multicolumn{1}{c|}{succ} & \multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{000} & \multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0101111} & FENCE.I \\ +\multicolumn{1}{c|}{0001111} & FENCE \\ \cline{2-11} & -\multicolumn{1}{|c|}{00000} & +\multicolumn{1}{|c|}{0000} & +\multicolumn{4}{c|}{0000} & +\multicolumn{1}{c|}{0000} & \multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{000} & \multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101111} & FENCE \\ +\multicolumn{1}{c|}{0001111} & FENCE.I \\ \cline{2-11} & -\multicolumn{1}{|c|}{00000} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{000} & \multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{000} & \multicolumn{1}{c|}{1110111} & SYSCALL \\ \cline{2-11} & -\multicolumn{1}{|c|}{00000} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{001} & \multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{001} & \multicolumn{1}{c|}{1110111} & BREAK \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{100} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1110111} & RDCYCLE rd \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{00000} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{100} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1110111} & RDTIME rd \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000010} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000010} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{100} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1110111} & RDINSTRET rd \\ \cline{2-11} @@ -505,179 +514,167 @@ \begin{center} \begin{tabular}{rccccccccccl} & -\instbitrange{31}{27} & -\instbitrange{26}{22} & -\instbitrange{21}{17} & -\instbit{16} & - & -\instbitrange{}{12} & -\instbitrange{11}{10} & -\instbit{9} & -\instbitrange{}{7} & +\multicolumn{1}{l}{\instbit{31}} & +\multicolumn{1}{r}{\instbit{27}} & +\instbit{26} & +\instbit{25} & +\multicolumn{2}{c}{\instbitrange{24}{20}} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbitrange{11}{7} & \instbitrange{6}{0} \\ \cline{2-11} + + & -\multicolumn{9}{|c|}{jump target} & -\multicolumn{1}{c|}{opcode} & J-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{upper immediate} & -\multicolumn{1}{c|}{opcode} & U-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm[11:7]} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & I-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{imm[11:7]} & +\multicolumn{4}{|c|}{funct7} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & B-type \\ +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{opcode} & R-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{6}{c|}{funct10} & -\multicolumn{1}{c|}{opcode} & R-type \\ +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{opcode} & I-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{3}{c|}{funct5} & -\multicolumn{1}{c|}{opcode} & R4-type \\ +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{opcode} & S-type \\ \cline{2-11} - + & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV64I Instruction Subset (in addition to RV32I)} & \\ +\multicolumn{10}{c}{\bf RV64I Base Instruction Set (in addition to RV32I)} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{110} & -\multicolumn{1}{c|}{0000011} & LWU rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000011} & LWU rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0000011} & LD rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000011} & LD rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0100011} & SD rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{0100011} & SD rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0011011} & ADDIW rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0011011} & ADDIW rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100000} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{3}{c|}{0000000} & -\multicolumn{2}{c|}{shamtw} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0011011} & SLLIW rd,rs1,shamtw \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0011011} & SLLIW rd,rs1,shamt \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{3}{c|}{0000000} & -\multicolumn{2}{c|}{shamtw} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0011011} & SRLIW rd,rs1,shamtw \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0011011} & SRLIW rd,rs1,shamt \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100000} & +\multicolumn{2}{c|}{shamt} & \multicolumn{1}{c|}{rs1} & -\multicolumn{3}{c|}{0000010} & -\multicolumn{2}{c|}{shamtw} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0011011} & SRAIW rd,rs1,shamtw \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0011011} & SRAIW rd,rs1,shamt \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & ADDW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & SUBW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & SLLW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{101} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & SRLW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{101} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & SRAW rd,rs1,rs2 \\ \cline{2-11} @@ -685,86 +682,86 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV32M Instruction Subset} & \\ +\multicolumn{10}{c}{\bf RV32M Standard Extension} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & MUL rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{001} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & MULH rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{010} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & MULHSU rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{011} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & MULHU rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{100} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & DIV rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{101} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & DIVU rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{110} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & REM rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{111} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0110011} & REMU rd,rs1,rs2 \\ \cline{2-11} @@ -772,56 +769,56 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV64M Instruction Subset (in addition to RV32M)} & \\ +\multicolumn{10}{c}{\bf RV64M Standard Extension (in addition to RV32M)} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & MULW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{100} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & DIVW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{101} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & DIVUW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{110} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & REMW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{111} & +\multicolumn{1}{c|}{111} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{0111011} & REMUW rd,rs1,rs2 \\ \cline{2-11} @@ -829,107 +826,139 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV32A Instruction Subset} & \\ +\multicolumn{10}{c}{\bf RV32A Standard Extension} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00010} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOADD.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & LR.W rd,rs1 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00011} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOSWAP.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & SC.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00001} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000010} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOAND.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOSWAP.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000011} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOOR.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOADD.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000100} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMIN.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOXOR.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{01100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000101} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMAX.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOAND.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{01000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000110} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMINU.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOOR.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{10000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000111} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMAXU.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMIN.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{10100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & LR.W rd,rs1 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMAX.W rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{2}{|c|}{11000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMINU.W rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{11100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000001} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & SC.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMAXU.W rd,rs1,rs2 \\ \cline{2-11} @@ -948,463 +977,462 @@ \begin{center} \begin{tabular}{rccccccccccl} & -\instbitrange{31}{27} & -\instbitrange{26}{22} & -\instbitrange{21}{17} & -\instbit{16} & - & -\instbitrange{}{12} & -\instbitrange{11}{10} & -\instbit{9} & -\instbitrange{}{7} & +\multicolumn{1}{l}{\instbit{31}} & +\multicolumn{1}{r}{\instbit{27}} & +\instbit{26} & +\instbit{25} & +\multicolumn{2}{c}{\instbitrange{24}{20}} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbitrange{11}{7} & \instbitrange{6}{0} \\ \cline{2-11} + + & -\multicolumn{9}{|c|}{jump target} & -\multicolumn{1}{c|}{opcode} & J-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{upper immediate} & -\multicolumn{1}{c|}{opcode} & U-type \\ +\multicolumn{4}{|c|}{funct7} & +\multicolumn{2}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{opcode} & R-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm[11:7]} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{opcode} & I-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{imm[11:7]} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & B-type \\ +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{opcode} & S-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{6}{c|}{funct10} & -\multicolumn{1}{c|}{opcode} & R-type \\ -\cline{2-11} +\multicolumn{10}{c}{} & \\ & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{3}{c|}{funct5} & -\multicolumn{1}{c|}{opcode} & R4-type \\ +\multicolumn{10}{c}{\bf RV64A Standard Extension (in addition to RV32A)} & \\ \cline{2-11} & -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf RV64A Instruction Subset (in addition to RV32A)} & \\ +\multicolumn{2}{|c|}{00010} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & LR.D rd,rs1 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00011} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOADD.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & SC.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00001} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOSWAP.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOSWAP.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000010} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOAND.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOADD.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{00100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000011} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOOR.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOXOR.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{01100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000100} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMIN.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOAND.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{01000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000101} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMAX.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOOR.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{10000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000110} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMINU.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMIN.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{10100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000111} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMAXU.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMAX.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{11000} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & LR.D rd,rs1 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMINU.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{11100} & +\multicolumn{1}{c|}{aq} & +\multicolumn{1}{c|}{rl} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000001} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & SC.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0101111} & AMOMAXU.D rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV32F Instruction Subset} & \\ +\multicolumn{10}{c}{\bf RV32F Standard Extension} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0000111} & FLW rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000111} & FLW rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0100111} & FSW rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{0100111} & FSW rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00000} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FADD.S rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000100} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00001} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSUB.S rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0001000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00010} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMUL.S rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0001100} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00011} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FDIV.S rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0010000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{00100} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSQRT.S rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1100000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11000} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMIN.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1100100} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11001} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMAX.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{00} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1000011} & FMADD.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{00} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1000111} & FMSUB.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{00} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1001011} & FNMSUB.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{00} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1001111} & FNMADD.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0010100} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSGNJ.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0011000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSGNJN.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0011100} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSGNJX.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0111000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01110} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.S.W rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0111100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01111} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.S.WU rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1111000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMV.S.X rd,rs1 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0101000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01010} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.W.S rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0101100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01011} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.WU.S rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1110000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11100} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMV.X.S rd,rs1 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1010100} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FEQ.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1011000} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FLT.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1011100} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FLE.S rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1111100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSSR rd,rs1 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{00000} & +\multicolumn{4}{|c|}{1110100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FRSR rd \\ \cline{2-11} @@ -1424,55 +1452,35 @@ \begin{center} \begin{tabular}{rccccccccccl} & -\instbitrange{31}{27} & -\instbitrange{26}{22} & -\instbitrange{21}{17} & -\instbit{16} & - & -\instbitrange{}{12} & -\instbitrange{11}{10} & -\instbit{9} & -\instbitrange{}{7} & +\multicolumn{1}{l}{\instbit{31}} & +\multicolumn{1}{r}{\instbit{27}} & +\instbit{26} & +\instbit{25} & +\multicolumn{2}{c}{\instbitrange{24}{20}} & +\instbitrange{19}{15} & +\instbitrange{14}{12} & +\instbitrange{11}{7} & \instbitrange{6}{0} \\ \cline{2-11} + + & -\multicolumn{9}{|c|}{jump target} & -\multicolumn{1}{c|}{opcode} & J-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{upper immediate} & -\multicolumn{1}{c|}{opcode} & U-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm[11:7]} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & I-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{imm[11:7]} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & B-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{funct7} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{6}{c|}{funct10} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{opcode} & R-type \\ \cline{2-11} + + & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{funct2} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{3}{c|}{funct5} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{opcode} & R4-type \\ \cline{2-11} @@ -1480,50 +1488,46 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV64F Instruction Subset (in addition to RV32F)} & \\ +\multicolumn{10}{c}{\bf RV64F Standard Extension (in addition to RV32F)} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0110000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01100} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.S.L rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0110100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01101} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.S.LU rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100000} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01000} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.L.S rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01001} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.LU.S rd,rs1,rm \\ \cline{2-11} @@ -1531,256 +1535,239 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV32D Instruction Subset} & \\ +\multicolumn{10}{c}{\bf RV32D Standard Extension} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0000111} & FLD rd,rs1,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{0000111} & FLD rd,rs1,imm \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{4}{|c|}{imm[11:5]} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0100111} & FSD rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{imm[4:0]} & +\multicolumn{1}{c|}{0100111} & FSD rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00000} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FADD.D rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0000101} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00001} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSUB.D rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0001001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00010} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMUL.D rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0001101} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00011} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FDIV.D rd,rs1,rs2,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0010001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{00100} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSQRT.D rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1100001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11000} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMIN.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1100101} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11001} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMAX.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{01} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1000011} & FMADD.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{01} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1000111} & FMSUB.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{01} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1001011} & FNMSUB.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{2}{|c|}{rs3} & +\multicolumn{2}{c|}{01} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1001111} & FNMADD.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0010101} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSGNJ.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0011001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSGNJN.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0011101} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FSGNJX.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0111001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01110} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.D.W rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0111101} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01111} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.D.WU rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0101001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01010} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.W.D rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0101101} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01011} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.WU.D rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1010101} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FEQ.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1011001} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FLT.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1011101} & +\multicolumn{2}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FLE.D rd,rs1,rs2 \\ \cline{2-11} @@ -1788,94 +1775,86 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf RV64D Instruction Subset (in addition to RV32D)} & \\ +\multicolumn{10}{c}{\bf RV64D Standard Extension (in addition to RV32D)} & \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0110001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01100} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.D.L rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0110101} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01101} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.D.LU rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1111001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMV.D.X rd,rs1 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01000} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.L.D rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{0100101} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01001} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.LU.D rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1110001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11100} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FMV.X.D rd,rs1 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1000100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{10001} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.S.D rd,rs1,rm \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{4}{|c|}{1000001} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{10000} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{rm} & +\multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{1010011} & FCVT.D.S rd,rs1,rm \\ \cline{2-11} @@ -7,201 +7,196 @@ # <args> is one of rd, rs1, rs2, rs3, imm25, imm20, imm12, imm12lo, imm12hi, # shamtw, shamt, rm -j imm25 6..2=0x1A 1..0=3 -jal imm25 6..2=0x1B 1..0=3 +jal rd jimm20 6..2=0x19 1..0=3 -jalr rd rs1 imm12 9..7=0 6..2=0x19 1..0=3 +jalr rd rs1 imm12 14..12=0 6..2=0x1b 1..0=3 -beq imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x18 1..0=3 -bne imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x18 1..0=3 -blt imm12hi rs1 rs2 imm12lo 9..7=4 6..2=0x18 1..0=3 -bge imm12hi rs1 rs2 imm12lo 9..7=5 6..2=0x18 1..0=3 -bltu imm12hi rs1 rs2 imm12lo 9..7=6 6..2=0x18 1..0=3 -bgeu imm12hi rs1 rs2 imm12lo 9..7=7 6..2=0x18 1..0=3 +beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 +bne bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3 +blt bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3 +bge bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3 +bltu bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3 +bgeu bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3 lui rd imm20 6..2=0x0D 1..0=3 auipc rd imm20 6..2=0x05 1..0=3 -addi rd rs1 imm12 9..7=0 6..2=0x04 1..0=3 -slli rd rs1 21..17=0 16=0 shamt 9..7=1 6..2=0x04 1..0=3 -slti rd rs1 imm12 9..7=2 6..2=0x04 1..0=3 -sltiu rd rs1 imm12 9..7=3 6..2=0x04 1..0=3 -xori rd rs1 imm12 9..7=4 6..2=0x04 1..0=3 -srli rd rs1 21..17=0 16=0 shamt 9..7=5 6..2=0x04 1..0=3 -srai rd rs1 21..17=0 16=1 shamt 9..7=5 6..2=0x04 1..0=3 -ori rd rs1 imm12 9..7=6 6..2=0x04 1..0=3 -andi rd rs1 imm12 9..7=7 6..2=0x04 1..0=3 - -add rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0C 1..0=3 -sub rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0C 1..0=3 -sll rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0C 1..0=3 -slt rd rs1 rs2 16=0 15..10=0 9..7=2 6..2=0x0C 1..0=3 -sltu rd rs1 rs2 16=0 15..10=0 9..7=3 6..2=0x0C 1..0=3 -xor rd rs1 rs2 16=0 15..10=0 9..7=4 6..2=0x0C 1..0=3 -srl rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0C 1..0=3 -sra rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0C 1..0=3 -or rd rs1 rs2 16=0 15..10=0 9..7=6 6..2=0x0C 1..0=3 -and rd rs1 rs2 16=0 15..10=0 9..7=7 6..2=0x0C 1..0=3 - -mul rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0C 1..0=3 -mulh rd rs1 rs2 16=0 15..10=1 9..7=1 6..2=0x0C 1..0=3 -mulhsu rd rs1 rs2 16=0 15..10=1 9..7=2 6..2=0x0C 1..0=3 -mulhu rd rs1 rs2 16=0 15..10=1 9..7=3 6..2=0x0C 1..0=3 -div rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0C 1..0=3 -divu rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0C 1..0=3 -rem rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0C 1..0=3 -remu rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0C 1..0=3 - -addiw rd rs1 imm12 9..7=0 6..2=0x06 1..0=3 -slliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=1 6..2=0x06 1..0=3 -srliw rd rs1 21..17=0 16=0 15=0 shamtw 9..7=5 6..2=0x06 1..0=3 -sraiw rd rs1 21..17=0 16=1 15=0 shamtw 9..7=5 6..2=0x06 1..0=3 - -addw rd rs1 rs2 16=0 15..10=0 9..7=0 6..2=0x0E 1..0=3 -subw rd rs1 rs2 16=1 15..10=0 9..7=0 6..2=0x0E 1..0=3 -sllw rd rs1 rs2 16=0 15..10=0 9..7=1 6..2=0x0E 1..0=3 -srlw rd rs1 rs2 16=0 15..10=0 9..7=5 6..2=0x0E 1..0=3 -sraw rd rs1 rs2 16=1 15..10=0 9..7=5 6..2=0x0E 1..0=3 - -mulw rd rs1 rs2 16=0 15..10=1 9..7=0 6..2=0x0E 1..0=3 -divw rd rs1 rs2 16=0 15..10=1 9..7=4 6..2=0x0E 1..0=3 -divuw rd rs1 rs2 16=0 15..10=1 9..7=5 6..2=0x0E 1..0=3 -remw rd rs1 rs2 16=0 15..10=1 9..7=6 6..2=0x0E 1..0=3 -remuw rd rs1 rs2 16=0 15..10=1 9..7=7 6..2=0x0E 1..0=3 - -lb rd rs1 imm12 9..7=0 6..2=0x00 1..0=3 -lh rd rs1 imm12 9..7=1 6..2=0x00 1..0=3 -lw rd rs1 imm12 9..7=2 6..2=0x00 1..0=3 -ld rd rs1 imm12 9..7=3 6..2=0x00 1..0=3 -lbu rd rs1 imm12 9..7=4 6..2=0x00 1..0=3 -lhu rd rs1 imm12 9..7=5 6..2=0x00 1..0=3 -lwu rd rs1 imm12 9..7=6 6..2=0x00 1..0=3 - -# XXX If you add new store instructions, make sure to modify tc-riscv.c and -# elfxx-riscv.c to detect them; the split immediate is handled therein. -# search for MATCH_SW and continue this inglorious hack in the obvious way. -sb imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3 -sh imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3 -sw imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3 -sd imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x08 1..0=3 - -amoadd.w rd rs1 rs2 16..10=0 9..7=2 6..2=0x0A 1..0=3 -amoswap.w rd rs1 rs2 16..10=1 9..7=2 6..2=0x0A 1..0=3 -amoand.w rd rs1 rs2 16..10=2 9..7=2 6..2=0x0A 1..0=3 -amoor.w rd rs1 rs2 16..10=3 9..7=2 6..2=0x0A 1..0=3 -amomin.w rd rs1 rs2 16..10=4 9..7=2 6..2=0x0A 1..0=3 -amomax.w rd rs1 rs2 16..10=5 9..7=2 6..2=0x0A 1..0=3 -amominu.w rd rs1 rs2 16..10=6 9..7=2 6..2=0x0A 1..0=3 -amomaxu.w rd rs1 rs2 16..10=7 9..7=2 6..2=0x0A 1..0=3 +addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 +slli rd rs1 31..26=16 shamt 14..12=1 6..2=0x04 1..0=3 +slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 +sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 +xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 +srli rd rs1 31..26=0 shamt 14..12=5 6..2=0x04 1..0=3 +srai rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3 +ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 +andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 + +add rd rs1 rs2 31..25=0 14..12=0 6..2=0x0C 1..0=3 +sub rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3 +sll rd rs1 rs2 31..25=0 14..12=1 6..2=0x0C 1..0=3 +slt rd rs1 rs2 31..25=0 14..12=2 6..2=0x0C 1..0=3 +sltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x0C 1..0=3 +xor rd rs1 rs2 31..25=0 14..12=4 6..2=0x0C 1..0=3 +srl rd rs1 rs2 31..25=0 14..12=5 6..2=0x0C 1..0=3 +sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 +or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 +and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 + +mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 +mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 +mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 +mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 +div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 +divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 +rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 +remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 + +addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 +slliw rd rs1 31..25=32 shamtw 14..12=1 6..2=0x06 1..0=3 +srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +sraiw rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3 + +addw rd rs1 rs2 31..25=0 14..12=0 6..2=0x0E 1..0=3 +subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 +sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 +srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 +sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 + +mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 +divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 +divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 +remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 +remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 + +lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3 +lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3 +lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3 +ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 +lbu rd rs1 imm12 14..12=4 6..2=0x00 1..0=3 +lhu rd rs1 imm12 14..12=5 6..2=0x00 1..0=3 +lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 + +sb imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3 +sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3 +sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3 +sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 + +amoadd.w rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoxor.w rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoor.w rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoand.w rd rs1 rs2 aqrl 31..29=3 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomin.w rd rs1 rs2 aqrl 31..29=4 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomax.w rd rs1 rs2 aqrl 31..29=5 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amominu.w rd rs1 rs2 aqrl 31..29=6 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomaxu.w rd rs1 rs2 aqrl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoswap.w rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 +lr.w rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 +sc.w rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 -amoadd.d rd rs1 rs2 16..10=0 9..7=3 6..2=0x0A 1..0=3 -amoswap.d rd rs1 rs2 16..10=1 9..7=3 6..2=0x0A 1..0=3 -amoand.d rd rs1 rs2 16..10=2 9..7=3 6..2=0x0A 1..0=3 -amoor.d rd rs1 rs2 16..10=3 9..7=3 6..2=0x0A 1..0=3 -amomin.d rd rs1 rs2 16..10=4 9..7=3 6..2=0x0A 1..0=3 -amomax.d rd rs1 rs2 16..10=5 9..7=3 6..2=0x0A 1..0=3 -amominu.d rd rs1 rs2 16..10=6 9..7=3 6..2=0x0A 1..0=3 -amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3 - -lr.w rd rs1 21..17=0 16=1 15..10=0 9..7=2 6..2=0x0A 1..0=3 -lr.d rd rs1 21..17=0 16=1 15..10=0 9..7=3 6..2=0x0A 1..0=3 -sc.w rd rs1 rs2 16=1 15..10=1 9..7=2 6..2=0x0A 1..0=3 -sc.d rd rs1 rs2 16=1 15..10=1 9..7=3 6..2=0x0A 1..0=3 - -fence.i 31..10=ignore 9..7=1 6..2=0x0B 1..0=3 -fence 31..10=ignore 9..7=2 6..2=0x0B 1..0=3 -fence.v.l 31..10=ignore 9..7=4 6..2=0x0B 1..0=3 -fence.v.g 31..10=ignore 9..7=5 6..2=0x0B 1..0=3 - -syscall 31..27=0 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1D 1..0=3 -break 31..27=0 26..22=0 21..17=0 16..10=0 9..7=1 6..2=0x1D 1..0=3 -rdcycle rd 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1D 1..0=3 -rdtime rd 26..22=0 21..17=0 16..10=1 9..7=4 6..2=0x1D 1..0=3 -rdinstret rd 26..22=0 21..17=0 16..10=2 9..7=4 6..2=0x1D 1..0=3 +amoadd.d rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoxor.d rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoor.d rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoand.d rd rs1 rs2 aqrl 31..29=3 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomin.d rd rs1 rs2 aqrl 31..29=4 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomax.d rd rs1 rs2 aqrl 31..29=5 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amominu.d rd rs1 rs2 aqrl 31..29=6 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomaxu.d rd rs1 rs2 aqrl 31..29=7 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoswap.d rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 +lr.d rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 +sc.d rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 + +fence 31..28=ignore pred succ 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3 +fence.i 31..28=ignore 27..20=ignore 19..15=ignore 14..12=1 11..7=ignore 6..2=0x03 1..0=3 + +syscall 11..7=0 19..15=0 24..20=0 31..25=0 14..12=0 6..2=0x1D 1..0=3 +break 11..7=0 19..15=0 24..20=0 31..25=0 14..12=1 6..2=0x1D 1..0=3 +rdcycle rd 19..15=0 24..20=0 31..25=0 14..12=4 6..2=0x1D 1..0=3 +rdtime rd 19..15=0 24..20=0 31..25=1 14..12=4 6..2=0x1D 1..0=3 +rdinstret rd 19..15=0 24..20=0 31..25=2 14..12=4 6..2=0x1D 1..0=3 # SUPERVISOR -mtpcr rd rs1 rs2 16..10=0 9..7=0 6..2=0x1C 1..0=3 -mfpcr rd rs1 21..17=0 16..10=0 9..7=1 6..2=0x1C 1..0=3 -setpcr rd rs1 imm12 9..7=2 6..2=0x1C 1..0=3 -clearpcr rd rs1 imm12 9..7=3 6..2=0x1C 1..0=3 -eret 31..27=0 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1C 1..0=3 +mtpcr rd rs1 rs2 31..25=0 14..12=0 6..2=0x1C 1..0=3 +mfpcr rd rs1 24..20=0 31..25=0 14..12=1 6..2=0x1C 1..0=3 +setpcr rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 +clearpcr rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 +eret 11..7=0 19..15=0 24..20=0 31..25=0 14..12=4 6..2=0x1C 1..0=3 # 0x7C-0x7F are reserved for >32b instructions -fadd.s rd rs1 rs2 16..12=0 rm 8..7=0 6..2=0x14 1..0=3 -fsub.s rd rs1 rs2 16..12=1 rm 8..7=0 6..2=0x14 1..0=3 -fmul.s rd rs1 rs2 16..12=2 rm 8..7=0 6..2=0x14 1..0=3 -fdiv.s rd rs1 rs2 16..12=3 rm 8..7=0 6..2=0x14 1..0=3 -fsqrt.s rd rs1 21..17=0 16..12=4 rm 8..7=0 6..2=0x14 1..0=3 -fsgnj.s rd rs1 rs2 16..12=5 11..9=0 8..7=0 6..2=0x14 1..0=3 -fsgnjn.s rd rs1 rs2 16..12=6 11..9=0 8..7=0 6..2=0x14 1..0=3 -fsgnjx.s rd rs1 rs2 16..12=7 11..9=0 8..7=0 6..2=0x14 1..0=3 - -fadd.d rd rs1 rs2 16..12=0x0 rm 8..7=1 6..2=0x14 1..0=3 -fsub.d rd rs1 rs2 16..12=0x1 rm 8..7=1 6..2=0x14 1..0=3 -fmul.d rd rs1 rs2 16..12=0x2 rm 8..7=1 6..2=0x14 1..0=3 -fdiv.d rd rs1 rs2 16..12=0x3 rm 8..7=1 6..2=0x14 1..0=3 -fsqrt.d rd rs1 21..17=0 16..12=0x4 rm 8..7=1 6..2=0x14 1..0=3 -fsgnj.d rd rs1 rs2 16..12=0x5 11..9=0 8..7=1 6..2=0x14 1..0=3 -fsgnjn.d rd rs1 rs2 16..12=0x6 11..9=0 8..7=1 6..2=0x14 1..0=3 -fsgnjx.d rd rs1 rs2 16..12=0x7 11..9=0 8..7=1 6..2=0x14 1..0=3 - -fcvt.l.s rd rs1 21..17=0 16..12=0x8 rm 8..7=0 6..2=0x14 1..0=3 -fcvt.lu.s rd rs1 21..17=0 16..12=0x9 rm 8..7=0 6..2=0x14 1..0=3 -fcvt.w.s rd rs1 21..17=0 16..12=0xA rm 8..7=0 6..2=0x14 1..0=3 -fcvt.wu.s rd rs1 21..17=0 16..12=0xB rm 8..7=0 6..2=0x14 1..0=3 - -fcvt.l.d rd rs1 21..17=0 16..12=0x8 rm 8..7=1 6..2=0x14 1..0=3 -fcvt.lu.d rd rs1 21..17=0 16..12=0x9 rm 8..7=1 6..2=0x14 1..0=3 -fcvt.w.d rd rs1 21..17=0 16..12=0xA rm 8..7=1 6..2=0x14 1..0=3 -fcvt.wu.d rd rs1 21..17=0 16..12=0xB rm 8..7=1 6..2=0x14 1..0=3 - -fcvt.s.l rd rs1 21..17=0 16..12=0xC rm 8..7=0 6..2=0x14 1..0=3 -fcvt.s.lu rd rs1 21..17=0 16..12=0xD rm 8..7=0 6..2=0x14 1..0=3 -fcvt.s.w rd rs1 21..17=0 16..12=0xE rm 8..7=0 6..2=0x14 1..0=3 -fcvt.s.wu rd rs1 21..17=0 16..12=0xF rm 8..7=0 6..2=0x14 1..0=3 - -fcvt.d.l rd rs1 21..17=0 16..12=0xC rm 8..7=1 6..2=0x14 1..0=3 -fcvt.d.lu rd rs1 21..17=0 16..12=0xD rm 8..7=1 6..2=0x14 1..0=3 -fcvt.d.w rd rs1 21..17=0 16..12=0xE rm 8..7=1 6..2=0x14 1..0=3 -fcvt.d.wu rd rs1 21..17=0 16..12=0xF rm 8..7=1 6..2=0x14 1..0=3 - -fcvt.s.d rd rs1 21..17=0 16..14=0x4 13..12=1 rm 8..7=0 6..2=0x14 1..0=3 -fcvt.d.s rd rs1 21..17=0 16..14=0x4 13..12=0 rm 8..7=1 6..2=0x14 1..0=3 - -feq.s rd rs1 rs2 16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3 -flt.s rd rs1 rs2 16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3 -fle.s rd rs1 rs2 16..12=0x17 11..9=0 8..7=0 6..2=0x14 1..0=3 - -feq.d rd rs1 rs2 16..12=0x15 11..9=0 8..7=1 6..2=0x14 1..0=3 -flt.d rd rs1 rs2 16..12=0x16 11..9=0 8..7=1 6..2=0x14 1..0=3 -fle.d rd rs1 rs2 16..12=0x17 11..9=0 8..7=1 6..2=0x14 1..0=3 - -fmin.s rd rs1 rs2 16..12=0x18 11..9=0 8..7=0 6..2=0x14 1..0=3 -fmax.s rd rs1 rs2 16..12=0x19 11..9=0 8..7=0 6..2=0x14 1..0=3 - -fmin.d rd rs1 rs2 16..12=0x18 11..9=0 8..7=1 6..2=0x14 1..0=3 -fmax.d rd rs1 rs2 16..12=0x19 11..9=0 8..7=1 6..2=0x14 1..0=3 - -fmv.x.s rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=0 6..2=0x14 1..0=3 -fmv.x.d rd rs1 21..17=0 16..12=0x1C 11..9=0 8..7=1 6..2=0x14 1..0=3 -frsr rd 26..22=0 21..17=0 16..12=0x1D 11..9=0 8..7=0 6..2=0x14 1..0=3 -fmv.s.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=0 6..2=0x14 1..0=3 -fmv.d.x rd rs1 21..17=0 16..12=0x1E 11..9=0 8..7=1 6..2=0x14 1..0=3 -fssr rd rs1 21..17=0 16..12=0x1F 11..9=0 8..7=0 6..2=0x14 1..0=3 - -flw rd rs1 imm12 9..7=2 6..2=0x01 1..0=3 -fld rd rs1 imm12 9..7=3 6..2=0x01 1..0=3 - -fsw imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x09 1..0=3 -fsd imm12hi rs1 rs2 imm12lo 9..7=3 6..2=0x09 1..0=3 - -fmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x10 1..0=3 -fmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x11 1..0=3 -fnmsub.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x12 1..0=3 -fnmadd.s rd rs1 rs2 rs3 rm 8..7=0 6..2=0x13 1..0=3 - -fmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x10 1..0=3 -fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 -fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 -fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 +fadd.s rd rs1 rs2 31..27=0x0 rm 26..25=0 6..2=0x14 1..0=3 +fsub.s rd rs1 rs2 31..27=0x1 rm 26..25=0 6..2=0x14 1..0=3 +fmul.s rd rs1 rs2 31..27=0x2 rm 26..25=0 6..2=0x14 1..0=3 +fdiv.s rd rs1 rs2 31..27=0x3 rm 26..25=0 6..2=0x14 1..0=3 +fsqrt.s rd rs1 24..20=0 31..27=0x4 rm 26..25=0 6..2=0x14 1..0=3 +fsgnj.s rd rs1 rs2 31..27=0x5 14..12=0 26..25=0 6..2=0x14 1..0=3 +fsgnjn.s rd rs1 rs2 31..27=0x6 14..12=0 26..25=0 6..2=0x14 1..0=3 +fsgnjx.s rd rs1 rs2 31..27=0x7 14..12=0 26..25=0 6..2=0x14 1..0=3 + +fadd.d rd rs1 rs2 31..27=0x0 rm 26..25=1 6..2=0x14 1..0=3 +fsub.d rd rs1 rs2 31..27=0x1 rm 26..25=1 6..2=0x14 1..0=3 +fmul.d rd rs1 rs2 31..27=0x2 rm 26..25=1 6..2=0x14 1..0=3 +fdiv.d rd rs1 rs2 31..27=0x3 rm 26..25=1 6..2=0x14 1..0=3 +fsqrt.d rd rs1 24..20=0 31..27=0x4 rm 26..25=1 6..2=0x14 1..0=3 +fsgnj.d rd rs1 rs2 31..27=0x5 14..12=0 26..25=1 6..2=0x14 1..0=3 +fsgnjn.d rd rs1 rs2 31..27=0x6 14..12=0 26..25=1 6..2=0x14 1..0=3 +fsgnjx.d rd rs1 rs2 31..27=0x7 14..12=0 26..25=1 6..2=0x14 1..0=3 + +fcvt.l.s rd rs1 24..20=0 31..27=0x8 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.lu.s rd rs1 24..20=0 31..27=0x9 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.w.s rd rs1 24..20=0 31..27=0xA rm 26..25=0 6..2=0x14 1..0=3 +fcvt.wu.s rd rs1 24..20=0 31..27=0xB rm 26..25=0 6..2=0x14 1..0=3 + +fcvt.l.d rd rs1 24..20=0 31..27=0x8 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.lu.d rd rs1 24..20=0 31..27=0x9 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.w.d rd rs1 24..20=0 31..27=0xA rm 26..25=1 6..2=0x14 1..0=3 +fcvt.wu.d rd rs1 24..20=0 31..27=0xB rm 26..25=1 6..2=0x14 1..0=3 + +fcvt.s.l rd rs1 24..20=0 31..27=0xC rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.lu rd rs1 24..20=0 31..27=0xD rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.w rd rs1 24..20=0 31..27=0xE rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.wu rd rs1 24..20=0 31..27=0xF rm 26..25=0 6..2=0x14 1..0=3 + +fcvt.d.l rd rs1 24..20=0 31..27=0xC rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.lu rd rs1 24..20=0 31..27=0xD rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.w rd rs1 24..20=0 31..27=0xE rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.wu rd rs1 24..20=0 31..27=0xF rm 26..25=1 6..2=0x14 1..0=3 + +fcvt.s.d rd rs1 24..20=0 31..29=0x4 28..27=1 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.d.s rd rs1 24..20=0 31..29=0x4 28..27=0 rm 26..25=1 6..2=0x14 1..0=3 + +feq.s rd rs1 rs2 31..27=0x15 14..12=0 26..25=0 6..2=0x14 1..0=3 +flt.s rd rs1 rs2 31..27=0x16 14..12=0 26..25=0 6..2=0x14 1..0=3 +fle.s rd rs1 rs2 31..27=0x17 14..12=0 26..25=0 6..2=0x14 1..0=3 + +feq.d rd rs1 rs2 31..27=0x15 14..12=0 26..25=1 6..2=0x14 1..0=3 +flt.d rd rs1 rs2 31..27=0x16 14..12=0 26..25=1 6..2=0x14 1..0=3 +fle.d rd rs1 rs2 31..27=0x17 14..12=0 26..25=1 6..2=0x14 1..0=3 + +fmin.s rd rs1 rs2 31..27=0x18 14..12=0 26..25=0 6..2=0x14 1..0=3 +fmax.s rd rs1 rs2 31..27=0x19 14..12=0 26..25=0 6..2=0x14 1..0=3 + +fmin.d rd rs1 rs2 31..27=0x18 14..12=0 26..25=1 6..2=0x14 1..0=3 +fmax.d rd rs1 rs2 31..27=0x19 14..12=0 26..25=1 6..2=0x14 1..0=3 + +fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 +fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 +frsr rd 19..15=0 24..20=0 31..27=0x1D 14..12=0 26..25=0 6..2=0x14 1..0=3 +fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 +fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 +fssr rd rs1 24..20=0 31..27=0x1F 14..12=0 26..25=0 6..2=0x14 1..0=3 + +flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 +fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 + +fsw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x09 1..0=3 +fsd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x09 1..0=3 + +fmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x10 1..0=3 +fmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x11 1..0=3 +fnmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x12 1..0=3 +fnmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x13 1..0=3 + +fmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x10 1..0=3 +fmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x11 1..0=3 +fnmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x12 1..0=3 +fnmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x13 1..0=3 diff --git a/opcodes-custom b/opcodes-custom index f988cab..036bc4b 100644 --- a/opcodes-custom +++ b/opcodes-custom @@ -1,27 +1,27 @@ -custom0 rd rs1 imm12 9..7=0 6..2=0x02 1..0=3 -custom0.rs1 rd rs1 imm12 9..7=2 6..2=0x02 1..0=3 -custom0.rs1.rs2 rd rs1 imm12 9..7=3 6..2=0x02 1..0=3 -custom0.rd rd rs1 imm12 9..7=4 6..2=0x02 1..0=3 -custom0.rd.rs1 rd rs1 imm12 9..7=6 6..2=0x02 1..0=3 -custom0.rd.rs1.rs2 rd rs1 imm12 9..7=7 6..2=0x02 1..0=3 +custom0 rd rs1 imm12 14..12=0 6..2=0x02 1..0=3 +custom0.rs1 rd rs1 imm12 14..12=2 6..2=0x02 1..0=3 +custom0.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x02 1..0=3 +custom0.rd rd rs1 imm12 14..12=4 6..2=0x02 1..0=3 +custom0.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x02 1..0=3 +custom0.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x02 1..0=3 -custom1 rd rs1 imm12 9..7=0 6..2=0x03 1..0=3 -custom1.rs1 rd rs1 imm12 9..7=2 6..2=0x03 1..0=3 -custom1.rs1.rs2 rd rs1 imm12 9..7=3 6..2=0x03 1..0=3 -custom1.rd rd rs1 imm12 9..7=4 6..2=0x03 1..0=3 -custom1.rd.rs1 rd rs1 imm12 9..7=6 6..2=0x03 1..0=3 -custom1.rd.rs1.rs2 rd rs1 imm12 9..7=7 6..2=0x03 1..0=3 +custom1 rd rs1 imm12 14..12=0 6..2=0x0A 1..0=3 +custom1.rs1 rd rs1 imm12 14..12=2 6..2=0x0A 1..0=3 +custom1.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x0A 1..0=3 +custom1.rd rd rs1 imm12 14..12=4 6..2=0x0A 1..0=3 +custom1.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x0A 1..0=3 +custom1.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x0A 1..0=3 -custom2 rd rs1 imm12 9..7=0 6..2=0x15 1..0=3 -custom2.rs1 rd rs1 imm12 9..7=2 6..2=0x15 1..0=3 -custom2.rs1.rs2 rd rs1 imm12 9..7=3 6..2=0x15 1..0=3 -custom2.rd rd rs1 imm12 9..7=4 6..2=0x15 1..0=3 -custom2.rd.rs1 rd rs1 imm12 9..7=6 6..2=0x15 1..0=3 -custom2.rd.rs1.rs2 rd rs1 imm12 9..7=7 6..2=0x15 1..0=3 +custom2 rd rs1 imm12 14..12=0 6..2=0x16 1..0=3 +custom2.rs1 rd rs1 imm12 14..12=2 6..2=0x16 1..0=3 +custom2.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x16 1..0=3 +custom2.rd rd rs1 imm12 14..12=4 6..2=0x16 1..0=3 +custom2.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x16 1..0=3 +custom2.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x16 1..0=3 -custom3 rd rs1 imm12 9..7=0 6..2=0x1E 1..0=3 -custom3.rs1 rd rs1 imm12 9..7=2 6..2=0x1E 1..0=3 -custom3.rs1.rs2 rd rs1 imm12 9..7=3 6..2=0x1E 1..0=3 -custom3.rd rd rs1 imm12 9..7=4 6..2=0x1E 1..0=3 -custom3.rd.rs1 rd rs1 imm12 9..7=6 6..2=0x1E 1..0=3 -custom3.rd.rs1.rs2 rd rs1 imm12 9..7=7 6..2=0x1E 1..0=3 +custom3 rd rs1 imm12 14..12=0 6..2=0x1E 1..0=3 +custom3.rs1 rd rs1 imm12 14..12=2 6..2=0x1E 1..0=3 +custom3.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x1E 1..0=3 +custom3.rd rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3 +custom3.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x1E 1..0=3 +custom3.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x1E 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index 1132a3a..8a30566 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -10,20 +10,25 @@ mask = {} arguments = {} arglut = {} -arglut['rd'] = (31,27) -arglut['rs1'] = (26,22) -arglut['rs2'] = (21,17) -arglut['rs3'] = (16,12) -arglut['rm'] = (11,9) -arglut['imm25'] = (31,7) -arglut['imm20'] = (26,7) -arglut['imm12'] = (21,10) -arglut['imm12hi'] = (31,27) -arglut['imm12lo'] = (16,10) -arglut['shamt'] = (15,10) -arglut['shamtw'] = (14,10) -arglut['acclimm7'] = (16,10) -arglut['vseglen'] = (16,14) +arglut['rd'] = (11,7) +arglut['rs1'] = (19,15) +arglut['rs2'] = (24,20) +arglut['rs3'] = (31,27) +arglut['aqrl'] = (26,25) +arglut['pred'] = (27,24) +arglut['succ'] = (23,20) +arglut['rm'] = (14,12) +arglut['imm20'] = (31,12) +arglut['jimm20'] = (31,12) +arglut['imm12'] = (31,20) +arglut['imm12hi'] = (31,25) +arglut['bimm12hi'] = (31,25) +arglut['imm12lo'] = (11,7) +arglut['bimm12lo'] = (11,7) +arglut['shamt'] = (25,20) +arglut['shamtw'] = (24,20) +arglut['acclimm7'] = (26,20) +arglut['vseglen'] = (26,24) arglut['crd'] = (9,5) arglut['crs2'] = (9,5) @@ -36,41 +41,6 @@ arglut['cimm6'] = (15,10) arglut['cimm10'] = (14,5) arglut['cimm5'] = (9,5) -typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,,8=r4rm,9=rrm,10=b -typelut[0x03] = 3 -typelut[0x07] = 3 -typelut[0x13] = 3 -typelut[0x1B] = 3 -typelut[0x23] = 10 -typelut[0x27] = 10 -typelut[0x2B] = 4 -typelut[0x2F] = 4 -typelut[0x33] = 4 -typelut[0x37] = 2 -typelut[0x17] = 2 -typelut[0x3B] = 4 -typelut[0x43] = 8 -typelut[0x47] = 8 -typelut[0x4B] = 8 -typelut[0x4F] = 8 -typelut[0x53] = 9 -typelut[0x63] = 10 -typelut[0x67] = 1 -typelut[0x6B] = 3 -typelut[0x6F] = 1 -typelut[0x77] = 4 -typelut[0x7B] = 4 - -# XXX RVC -for i in range(0,3): - for j in range(0,8): - typelut[j*4+i] = 0 - -# vector opcodes -typelut[0x0B] = 4 -typelut[0x0F] = 4 -typelut[0x73] = 4 - opcode_base = 0 opcode_size = 7 funct_base = 7 @@ -95,11 +65,9 @@ def make_isasim(match, mask): def yank(num,start,len): return (num >> start) & ((1 << len) - 1) -def str_arg(arg0,arg1,match,arguments): +def str_arg(arg0,name,match,arguments): if arg0 in arguments: - return arg0 - elif arg1 in arguments: - return arg1 + return name or arg0 else: start = arglut[arg0][1] len = arglut[arg0][0] - arglut[arg0][1] + 1 @@ -110,7 +78,28 @@ def str_inst(name,arguments): if 'imm12hi' in arguments and 'imm12lo' in arguments: arguments.remove('imm12hi') arguments.remove('imm12lo') - arguments.append('imm12') + if 'bimm12hi' in arguments and 'bimm12lo' in arguments: + arguments.remove('bimm12hi') + arguments.remove('bimm12lo') + arguments.append('imm') + if 'imm12' in arguments: + arguments.remove('imm12') + arguments.append('imm') + if 'imm20' in arguments: + arguments.remove('imm20') + arguments.append('imm') + if 'jimm20' in arguments: + arguments.remove('jimm20') + arguments.append('imm') + if 'shamtw' in arguments: + arguments.remove('shamtw') + arguments.append('shamt') + if 'aqrl' in arguments: + arguments.remove('aqrl') + if 'pred' in arguments: + arguments.remove('pred') + if 'succ' in arguments: + arguments.remove('succ') for idx in range(len(arguments)): ret = ret + arguments[idx] if idx != len(arguments)-1: @@ -128,51 +117,74 @@ def print_unimp_type(name,match,arguments): 'UNIMP' \ ) -def print_j_type(name,match,arguments): +def print_u_type(name,match,arguments): print """ & -\\multicolumn{9}{|c|}{%s} & +\\multicolumn{8}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('imm25','',match,arguments), \ + str_arg('imm20','imm[31:12]',match,arguments), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) -def print_lui_type(name,match,arguments): +def print_uj_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & -\\multicolumn{8}{c|}{%s} & +\\multicolumn{8}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ + str_arg('jimm20','imm[20, 10:1, 11, 19:12]',match,arguments), \ str_arg('rd','',match,arguments), \ - str_arg('imm20','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) -def print_b_type(name,match,arguments): +def print_s_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & +\\multicolumn{4}{|c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{4}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('imm12hi','',match,arguments), \ + str_arg('imm12hi','imm[11:5]',match,arguments), \ + str_arg('rs2','',match,arguments), \ str_arg('rs1','',match,arguments), \ + binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('imm12lo','imm[4:0]',match,arguments), \ + binary(yank(match,opcode_base,opcode_size),opcode_size), \ + str_inst(name,arguments) \ + ) + +def print_sb_type(name,match,arguments): + print """ +& +\\multicolumn{4}{|c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-11} + """ % \ + ( \ + str_arg('bimm12hi','imm[12, 10:5]',match,arguments), \ str_arg('rs2','',match,arguments), \ - str_arg('imm12lo','',match,arguments), \ + str_arg('rs1','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('bimm12lo','imm[4:1, 11]',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) @@ -180,18 +192,18 @@ def print_b_type(name,match,arguments): def print_i_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & +\\multicolumn{6}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{5}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('rd','',match,arguments), \ + str_arg('imm12','imm[11:0]',match,arguments), \ str_arg('rs1','',match,arguments), \ - str_arg('imm12','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) @@ -199,20 +211,20 @@ def print_i_type(name,match,arguments): def print_ish_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & +\\multicolumn{3}{|c|}{%s} & \\multicolumn{3}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('rd','',match,arguments), \ + binary(yank(match,26,6),6), \ + str_arg('shamt','shamt',match,arguments), \ str_arg('rs1','',match,arguments), \ - binary(yank(match,16,6),6), \ - str_arg('shamt','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) @@ -220,20 +232,20 @@ def print_ish_type(name,match,arguments): def print_ishw_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{3}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & +\\multicolumn{4}{|c|}{%s} & \\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('rd','',match,arguments), \ + binary(yank(match,25,7),7), \ + str_arg('shamtw','shamt',match,arguments), \ str_arg('rs1','',match,arguments), \ - binary(yank(match,15,7),7), \ - str_arg('shamtw','',match,arguments), \ binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) @@ -241,20 +253,20 @@ def print_ishw_type(name,match,arguments): def print_r_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & +\\multicolumn{4}{|c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{4}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('rd','',match,arguments), \ - str_arg('rs1','',match,arguments), \ + binary(yank(match,25,7),7), \ str_arg('rs2','',match,arguments), \ - binary(yank(match,10,7),7), \ - binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('rs1','',match,arguments), \ + str_arg('rm','',match,arguments), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) @@ -262,71 +274,73 @@ def print_r_type(name,match,arguments): def print_r4_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{3}{c|}{%s} & -\\multicolumn{3}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('rd','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - str_arg('rs2','',match,arguments), \ str_arg('rs3','',match,arguments), \ - binary(yank(match,7,5),5), \ + binary(yank(match,25,2),2), \ + str_arg('rs2','',match,arguments), \ + str_arg('rs1','',match,arguments), \ + str_arg('rm','',match,arguments), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) -def print_r_rm_type(name,match,arguments): +def print_amo_type(name,match,arguments): print """ & -\\multicolumn{1}{|c|}{%s} & +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{aq} & +\\multicolumn{1}{c|}{rl} & +\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{3}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('rd','',match,arguments), \ - str_arg('rs1','',match,arguments), \ + binary(yank(match,27,5),5), \ str_arg('rs2','',match,arguments), \ - binary(yank(match,12,5),5), \ - str_arg('rm','',match,arguments), \ - binary(yank(match,7,2),2), \ + str_arg('rs1','',match,arguments), \ + binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) -def print_r4_rm_type(name,match,arguments): +def print_fence_type(name,match,arguments): print """ & \\multicolumn{1}{|c|}{%s} & +\\multicolumn{4}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & -\\multicolumn{3}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & \\multicolumn{1}{c|}{%s} & \\multicolumn{1}{c|}{%s} & %s \\\\ \\cline{2-11} """ % \ ( \ - str_arg('rd','',match,arguments), \ + binary(yank(match,28,4),4), \ + str_arg('pred','~~~pred~~~~',match,arguments), \ + str_arg('succ','',match,arguments), \ str_arg('rs1','',match,arguments), \ - str_arg('rs2','',match,arguments), \ - str_arg('rs3','',match,arguments), \ - str_arg('rm','',match,arguments), \ - binary(yank(match,7,2),2), \ + binary(yank(match,funct_base,funct_size),funct_size), \ + str_arg('rd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) -def print_header(): +def print_header(*types): print """ \\newpage @@ -335,58 +349,88 @@ def print_header(): \\begin{center} \\begin{tabular}{rccccccccccl} & -\\instbitrange{31}{27} & -\\instbitrange{26}{22} & -\\instbitrange{21}{17} & -\\instbit{16} & - & -\\instbitrange{}{12} & -\\instbitrange{11}{10} & -\\instbit{9} & -\\instbitrange{}{7} & +\\multicolumn{1}{l}{\\instbit{31}} & +\\multicolumn{1}{r}{\\instbit{27}} & +\\instbit{26} & +\\instbit{25} & +\\multicolumn{2}{c}{\\instbitrange{24}{20}} & +\\instbitrange{19}{15} & +\\instbitrange{14}{12} & +\\instbitrange{11}{7} & \\instbitrange{6}{0} \\\\ \\cline{2-11} +""" + if 'r' in types: + print """ & -\\multicolumn{9}{|c|}{jump target} & -\\multicolumn{1}{c|}{opcode} & J-type \\\\ +\\multicolumn{4}{|c|}{funct7} & +\\multicolumn{2}{c|}{rs2} & +\\multicolumn{1}{c|}{rs1} & +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{1}{c|}{rd} & +\\multicolumn{1}{c|}{opcode} & R-type \\\\ \\cline{2-11} +""" + if 'r4' in types: + print """ & -\\multicolumn{1}{|c|}{rd} & -\\multicolumn{8}{c|}{upper immediate} & -\\multicolumn{1}{c|}{opcode} & U-type \\\\ +\\multicolumn{2}{|c|}{rs3} & +\\multicolumn{2}{c|}{funct2} & +\\multicolumn{2}{c|}{rs2} & +\\multicolumn{1}{c|}{rs1} & +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{1}{c|}{rd} & +\\multicolumn{1}{c|}{opcode} & R4-type \\\\ \\cline{2-11} + """ + if 'i' in types: + print """ & -\\multicolumn{1}{|c|}{rd} & +\\multicolumn{6}{|c|}{imm[11:0]} & \\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{imm[11:7]} & -\\multicolumn{4}{c|}{imm[6:0]} & -\\multicolumn{2}{c|}{funct3} & +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{1}{c|}{rd} & \\multicolumn{1}{c|}{opcode} & I-type \\\\ \\cline{2-11} +""" + if 's' in types: + print """ & -\\multicolumn{1}{|c|}{imm[11:7]} & +\\multicolumn{4}{|c|}{imm[11:5]} & +\\multicolumn{2}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{rs2} & -\\multicolumn{4}{c|}{imm[6:0]} & -\\multicolumn{2}{c|}{funct3} & -\\multicolumn{1}{c|}{opcode} & B-type \\\\ +\\multicolumn{1}{c|}{imm[4:0]} & +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{1}{c|}{opcode} & S-type \\\\ \\cline{2-11} +""" + if 'sb' in types: + print """ & -\\multicolumn{1}{|c|}{rd} & +\\multicolumn{4}{|c|}{imm[12, 10:5]} & +\\multicolumn{2}{c|}{rs2} & \\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{rs2} & -\\multicolumn{6}{c|}{funct10} & -\\multicolumn{1}{c|}{opcode} & R-type \\\\ +\\multicolumn{1}{c|}{funct3} & +\\multicolumn{1}{c|}{imm[4:1, 11]} & +\\multicolumn{1}{c|}{opcode} & SB-type \\\\ \\cline{2-11} +""" + if 'u' in types: + print """ & -\\multicolumn{1}{|c|}{rd} & -\\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{rs2} & -\\multicolumn{3}{c|}{rs3} & -\\multicolumn{3}{c|}{funct5} & -\\multicolumn{1}{c|}{opcode} & R4-type \\\\ +\\multicolumn{8}{|c|}{imm[31:12]} & +\\multicolumn{1}{c|}{rd} & +\\multicolumn{1}{c|}{opcode} & U-type \\\\ \\cline{2-11} - """ +""" + if 'uj' in types: + print """ +& +\\multicolumn{8}{|c|}{imm[20, 10:1, 11, 19:12]} & +\\multicolumn{1}{c|}{rd} & +\\multicolumn{1}{c|}{opcode} & UJ-type \\\\ +\\cline{2-11} +""" def print_subtitle(title): print """ @@ -408,25 +452,26 @@ def print_footer(caption): """ % (caption and '\\caption{Instruction listing for RISC-V}' or '') def print_inst(n): - if 'shamt' in arguments[n]: + if n == 'fence' or n == 'fence.i': + print_fence_type(n, match[n], arguments[n]) + elif 'aqrl' in arguments[n]: + print_amo_type(n, match[n], arguments[n]) + elif 'shamt' in arguments[n]: print_ish_type(n, match[n], arguments[n]) elif 'shamtw' in arguments[n]: print_ishw_type(n, match[n], arguments[n]) - elif 'imm25' in arguments[n]: - print_j_type(n, match[n], arguments[n]) elif 'imm20' in arguments[n]: - print_lui_type(n, match[n], arguments[n]) + print_u_type(n, match[n], arguments[n]) + elif 'jimm20' in arguments[n]: + print_uj_type(n, match[n], arguments[n]) elif 'imm12' in arguments[n]: print_i_type(n, match[n], arguments[n]) elif 'imm12hi' in arguments[n]: - print_b_type(n, match[n], arguments[n]) - elif 'rs3' in arguments[n] and 'rm' in arguments[n]: - print_r4_rm_type(n, match[n], arguments[n]) + print_s_type(n, match[n], arguments[n]) + elif 'bimm12hi' in arguments[n]: + print_sb_type(n, match[n], arguments[n]) elif 'rs3' in arguments[n]: print_r4_type(n, match[n], arguments[n]) - elif 'rm' in arguments[n] or \ - filter(lambda x: x in n, ['fmin','fmax','fsgnj','fmv','feq','flt','fle','fssr','frsr']): - print_r_rm_type(n, match[n], arguments[n]) else: print_r_type(n, match[n], arguments[n]) @@ -435,39 +480,41 @@ def print_insts(*names): print_inst(n) def make_latex_table(): - print_header() - print_subtitle('RV32I Instruction Subset') + print_header('r','i','s','sb','u','uj') + print_subtitle('RV32I Base Instruction Set') print_insts('lui', 'auipc') - print_insts('j', 'jal', 'jalr', 'beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu') + print_insts('jal', 'jalr', 'beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu') print_insts('lb', 'lh', 'lw', 'lbu', 'lhu', 'sb', 'sh', 'sw') - print_insts('addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi') + print_insts('addi', 'slti', 'sltiu', 'xori', 'ori', 'andi', 'slli', 'srli', 'srai') print_insts('add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and') - print_insts('fence.i', 'fence') + print_insts('fence', 'fence.i') print_insts('syscall', 'break', 'rdcycle', 'rdtime', 'rdinstret') print_footer(0) - print_header() - print_subtitle('RV64I Instruction Subset (in addition to RV32I)') + print_header('r','a','i','s') + print_subtitle('RV64I Base Instruction Set (in addition to RV32I)') print_insts('lwu', 'ld', 'sd') print_insts('addiw', 'slliw', 'srliw', 'sraiw') print_insts('addw', 'subw', 'sllw', 'srlw', 'sraw') - print_subtitle('RV32M Instruction Subset') + print_subtitle('RV32M Standard Extension') print_insts('mul', 'mulh', 'mulhsu', 'mulhu') print_insts('div', 'divu', 'rem', 'remu') - print_subtitle('RV64M Instruction Subset (in addition to RV32M)') + print_subtitle('RV64M Standard Extension (in addition to RV32M)') print_insts('mulw', 'divw', 'divuw', 'remw', 'remuw') - print_subtitle('RV32A Instruction Subset') - print_insts('amoadd.w', 'amoswap.w', 'amoand.w', 'amoor.w') - print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w') + print_subtitle('RV32A Standard Extension') print_insts('lr.w', 'sc.w') + print_insts('amoswap.w') + print_insts('amoadd.w', 'amoxor.w', 'amoand.w', 'amoor.w') + print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w') print_footer(0) - print_header() - print_subtitle('RV64A Instruction Subset (in addition to RV32A)') - print_insts('amoadd.d', 'amoswap.d', 'amoand.d', 'amoor.d') - print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d') + print_header('r','a','i','s') + print_subtitle('RV64A Standard Extension (in addition to RV32A)') print_insts('lr.d', 'sc.d') - print_subtitle('RV32F Instruction Subset') + print_insts('amoswap.d') + print_insts('amoadd.d', 'amoxor.d', 'amoand.d', 'amoor.d') + print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d') + print_subtitle('RV32F Standard Extension') print_insts('flw', 'fsw') print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s', 'fmin.s', 'fmax.s') print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s') @@ -478,11 +525,11 @@ def make_latex_table(): print_insts('fssr', 'frsr') print_footer(0) - print_header() - print_subtitle('RV64F Instruction Subset (in addition to RV32F)') + print_header('r','r4') + print_subtitle('RV64F Standard Extension (in addition to RV32F)') print_insts('fcvt.s.l', 'fcvt.s.lu') print_insts('fcvt.l.s', 'fcvt.lu.s') - print_subtitle('RV32D Instruction Subset') + print_subtitle('RV32D Standard Extension') print_insts('fld', 'fsd') print_insts('fadd.d', 'fsub.d', 'fmul.d', 'fdiv.d', 'fsqrt.d', 'fmin.d', 'fmax.d') print_insts('fmadd.d', 'fmsub.d', 'fnmsub.d', 'fnmadd.d') @@ -490,25 +537,25 @@ def make_latex_table(): print_insts('fcvt.d.w', 'fcvt.d.wu') print_insts('fcvt.w.d', 'fcvt.wu.d') print_insts('feq.d', 'flt.d', 'fle.d') - print_subtitle('RV64D Instruction Subset (in addition to RV32D)') + print_subtitle('RV64D Standard Extension (in addition to RV32D)') print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x') print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d') print_insts('fcvt.s.d', 'fcvt.d.s') print_footer(1) -def print_verilog_insn(name): - s = "`define %-10s 32'b" % name.replace('.', '_').upper() +def print_chisel_insn(name): + s = " def %-18s = Bits(\"b" % name.replace('.', '_').upper() for i in range(31, -1, -1): if yank(mask[name], i, 1): s = '%s%d' % (s, yank(match[name], i, 1)) else: s = s + '?' - print s + print s + "\")" -def make_verilog(): - print '/* Automatically generated by parse-opcodes */' +def make_chisel(): + print ' /* Automatically generated by parse-opcodes */' for name in namelist: - print_verilog_insn(name) + print_chisel_insn(name) for line in sys.stdin: line = line.partition('#') @@ -571,8 +618,8 @@ for line in sys.stdin: if sys.argv[1] == '-tex': make_latex_table() -elif sys.argv[1] == '-verilog': - make_verilog() +elif sys.argv[1] == '-chisel': + make_chisel() elif sys.argv[1] == '-disasm': make_disasm_table(match,mask) elif sys.argv[1] == '-isasim': |