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author | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
commit | 36f37737b8241fca0e3a5a1d18555cb1d406cff8 (patch) | |
tree | 11f8479f434fee1da06be155edeff0528c7026b7 /rv_zks | |
parent | 71ecf3563997ea9e7e15a3295aecfe773ad9c04e (diff) | |
parent | bc92b799d9e96b53a0e57e738bff8f12e6e1fc2d (diff) | |
download | riscv-opcodes-incoresemi-migration-to-new-format.zip riscv-opcodes-incoresemi-migration-to-new-format.tar.gz riscv-opcodes-incoresemi-migration-to-new-format.tar.bz2 |
Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv-opcodes into incoresemi-migration-to-new-formatincoresemi-migration-to-new-format
Diffstat (limited to 'rv_zks')
-rw-r--r-- | rv_zks | 26 |
1 files changed, 26 insertions, 0 deletions
@@ -0,0 +1,26 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 + +# Scalar SM4 - RV32, RV64 +$import rv_zksed::sm4ed +$import rv_zksed::sm4ks + +# Scalar SM3 - RV32, RV64 +$import rv_zksh::sm3p0 +$import rv_zksh::sm3p1 + |