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| author | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-26 13:15:00 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-31 09:28:19 -0800 |
| commit | d4c61c70b7419d0f00d14091f1c8558a03a681df (patch) | |
| tree | bbab8de51d1a8c6326e2213f5c0a269b4efa4c88 /rv32_c_f | |
| parent | 5245976d913f1e9d73836043a632ad2791037055 (diff) | |
| download | riscv-opcodes-d4c61c70b7419d0f00d14091f1c8558a03a681df.zip riscv-opcodes-d4c61c70b7419d0f00d14091f1c8558a03a681df.tar.gz riscv-opcodes-d4c61c70b7419d0f00d14091f1c8558a03a681df.tar.bz2 | |
Add support for Svadu
The Svadu extension (https://github.com/riscv/riscv-svadu) adds the
HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the
A/D bits in the PTE. Provide the bit encodings for the HADE support.
Diffstat (limited to 'rv32_c_f')
0 files changed, 0 insertions, 0 deletions