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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 23:07:23 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 23:07:23 -0700 |
commit | 4ae1384438363dc00617ea73078fad8f31ee4865 (patch) | |
tree | 778c3583eb9ac3e9cdd8dbe581cb6ecd51bb229e /inst.chisel | |
parent | 07ad8b661d3938f3152478569affd563751435e6 (diff) | |
download | riscv-opcodes-4ae1384438363dc00617ea73078fad8f31ee4865.zip riscv-opcodes-4ae1384438363dc00617ea73078fad8f31ee4865.tar.gz riscv-opcodes-4ae1384438363dc00617ea73078fad8f31ee4865.tar.bz2 |
Add hcall instruction
Diffstat (limited to 'inst.chisel')
-rw-r--r-- | inst.chisel | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/inst.chisel b/inst.chisel index a4f876b..16ed411 100644 --- a/inst.chisel +++ b/inst.chisel @@ -90,6 +90,7 @@ object Instructions { def SBREAK = Bits("b00000000000100000000000001110011") def SRET = Bits("b00010000001000000000000001110011") def SFENCE_VM = Bits("b000100000100?????000000001110011") + def HCALL = Bits("b00010000000000000000000001110011") def MCALL = Bits("b00100000000000000000000001110011") def MRET = Bits("b00110000001000000000000001110011") def MRTS = Bits("b00110000100100000000000001110011") |