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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-01-21 14:42:52 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-01-21 14:43:10 -0800 |
| commit | 1b4f2b1e85d6623e64d4348ef1a912a3033d14ea (patch) | |
| tree | 0e7f95f87b78bcf71bc2cec82268519f0d342193 /inst.chisel | |
| parent | 714662af27924f1c3dbf81d700e67dfafa0367a0 (diff) | |
| download | riscv-opcodes-1b4f2b1e85d6623e64d4348ef1a912a3033d14ea.zip riscv-opcodes-1b4f2b1e85d6623e64d4348ef1a912a3033d14ea.tar.gz riscv-opcodes-1b4f2b1e85d6623e64d4348ef1a912a3033d14ea.tar.bz2 | |
Auto-generate exception cause numbers
Diffstat (limited to 'inst.chisel')
| -rw-r--r-- | inst.chisel | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/inst.chisel b/inst.chisel index a805101..c1dca0b 100644 --- a/inst.chisel +++ b/inst.chisel @@ -180,6 +180,36 @@ object Instructions { def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") } +object Causes { + val misaligned_fetch = 0x0 + val fault_fetch = 0x1 + val illegal_instruction = 0x2 + val privileged_instruction = 0x3 + val fp_disabled = 0x4 + val syscall = 0x6 + val breakpoint = 0x7 + val misaligned_load = 0x8 + val misaligned_store = 0x9 + val fault_load = 0xa + val fault_store = 0xb + val accelerator_disabled = 0xc + val all = { + val res = collection.mutable.ArrayBuffer[Int]() + res += misaligned_fetch + res += fault_fetch + res += illegal_instruction + res += privileged_instruction + res += fp_disabled + res += syscall + res += breakpoint + res += misaligned_load + res += misaligned_store + res += fault_load + res += fault_store + res += accelerator_disabled + res.toArray + } +} object CSRs { val fflags = 0x1 val frm = 0x2 |