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| author | Atul Khare <atulkhare@rivosinc.com> | 2023-07-07 10:47:46 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-07-12 17:12:19 -0700 |
| commit | 99d5c26cec50c6bd4ac6d409691e909ba37b20c4 (patch) | |
| tree | 5e0c51626fbdf895dcb0ab2f23c36c7ebd9a514a /constants.py | |
| parent | be53d2453ff46e13eba372de208f1c719635e67b (diff) | |
| download | riscv-opcodes-99d5c26cec50c6bd4ac6d409691e909ba37b20c4.zip riscv-opcodes-99d5c26cec50c6bd4ac6d409691e909ba37b20c4.tar.gz riscv-opcodes-99d5c26cec50c6bd4ac6d409691e909ba37b20c4.tar.bz2 | |
Add Smcdeleg CSR+constants
Adds CSR scountinhibit (0x120), MSTATEEN0.CD (bit 56), and siselect
range (0x40 - 0x5F).
Diffstat (limited to 'constants.py')
| -rw-r--r-- | constants.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/constants.py b/constants.py index 98c4b7c..d345454 100644 --- a/constants.py +++ b/constants.py @@ -108,6 +108,7 @@ csrs = [ (0x10D, 'sstateen1'), # Smstateen (0x10E, 'sstateen2'), # Smstateen (0x10F, 'sstateen3'), # Smstateen + (0x120, 'scountinhibit'), # Smcdeleg (0x140, 'sscratch'), (0x141, 'sepc'), (0x142, 'scause'), |