From 99d5c26cec50c6bd4ac6d409691e909ba37b20c4 Mon Sep 17 00:00:00 2001
From: Atul Khare <atulkhare@rivosinc.com>
Date: Fri, 7 Jul 2023 10:47:46 -0700
Subject: Add Smcdeleg CSR+constants

Adds CSR scountinhibit (0x120), MSTATEEN0.CD (bit 56), and siselect
range (0x40 - 0x5F).
---
 constants.py | 1 +
 1 file changed, 1 insertion(+)

(limited to 'constants.py')

diff --git a/constants.py b/constants.py
index 98c4b7c..d345454 100644
--- a/constants.py
+++ b/constants.py
@@ -108,6 +108,7 @@ csrs = [
   (0x10D, 'sstateen1'), # Smstateen
   (0x10E, 'sstateen2'), # Smstateen
   (0x10F, 'sstateen3'), # Smstateen
+  (0x120, 'scountinhibit'), # Smcdeleg
   (0x140, 'sscratch'),
   (0x141, 'sepc'),
   (0x142, 'scause'),
-- 
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