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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-13 20:10:10 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 18:23:12 -0700 |
| commit | 61a642421d7f82abf874d56513158d652124f246 (patch) | |
| tree | 139ee99407dc607e6c686a008adf9a961f4176f3 /Makefile | |
| parent | 73b3d3e819c341d76240365bc7c892fc686795fb (diff) | |
| download | riscv-opcodes-61a642421d7f82abf874d56513158d652124f246.zip riscv-opcodes-61a642421d7f82abf874d56513158d652124f246.tar.gz riscv-opcodes-61a642421d7f82abf874d56513158d652124f246.tar.bz2 | |
rvv: vector instruction encoding
add most of vector instruction encoding described in v-spec 0.7.
except for 'Zvamo' extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -6,13 +6,13 @@ FESVR_H := ../riscv-isa-sim/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom +ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse-opcodes encoding.h cp encoding.h $@ - cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom | ./parse-opcodes -c >> $@ + cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom opcodes-rvv | python ./parse-opcodes -c >> $@ inst.chisel: $(ALL_OPCODES) parse-opcodes cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-pseudo | ./parse-opcodes -chisel > $@ |