From 61a642421d7f82abf874d56513158d652124f246 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Mon, 13 May 2019 20:10:10 -0700 Subject: rvv: vector instruction encoding add most of vector instruction encoding described in v-spec 0.7. except for 'Zvamo' extension Signed-off-by: Chih-Min Chao --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index 4017c4a..1a6f0b1 100644 --- a/Makefile +++ b/Makefile @@ -6,13 +6,13 @@ FESVR_H := ../riscv-isa-sim/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom +ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse-opcodes encoding.h cp encoding.h $@ - cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom | ./parse-opcodes -c >> $@ + cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom opcodes-rvv | python ./parse-opcodes -c >> $@ inst.chisel: $(ALL_OPCODES) parse-opcodes cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-pseudo | ./parse-opcodes -chisel > $@ -- cgit v1.1