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| author | Andrew Waterman <andrew@sifive.com> | 2019-01-22 13:59:56 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-01-22 13:59:56 -0800 |
| commit | ec25bc8728fcdc3e960213ff85773efd61673aa8 (patch) | |
| tree | ea257f6ddeeca54dbf019362b61821d0dbe941b7 | |
| parent | 9d28c9a9a173f197b1983842caae550d60b36706 (diff) | |
| download | riscv-opcodes-ec25bc8728fcdc3e960213ff85773efd61673aa8.zip riscv-opcodes-ec25bc8728fcdc3e960213ff85773efd61673aa8.tar.gz riscv-opcodes-ec25bc8728fcdc3e960213ff85773efd61673aa8.tar.bz2 | |
Add tentative CSR assignment for fast-interrupt group's CLIC proposal
| -rwxr-xr-x | parse-opcodes | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/parse-opcodes b/parse-opcodes index 9881801..a2c5322 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -120,6 +120,23 @@ csrs = [ (0xA03, 'hideleg'), (0xA80, 'hgatp'), + # Tentative CSR assignment for CLIC + (0x007, 'utvt'), + (0x045, 'unxti'), + (0x046, 'uintstatus'), + (0x048, 'uscratchcsw'), + (0x049, 'uscratchcswl'), + (0x107, 'stvt'), + (0x145, 'snxti'), + (0x146, 'sintstatus'), + (0x148, 'sscratchcsw'), + (0x149, 'sscratchcswl'), + (0x307, 'mtvt'), + (0x345, 'mnxti'), + (0x346, 'mintstatus'), + (0x348, 'mscratchcsw'), + (0x349, 'mscratchcswl'), + # Standard Machine R/W (0x300, 'mstatus'), (0x301, 'misa'), |