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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-05 19:14:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-05 19:14:08 -0700 |
| commit | b32fad7bb845d5f81cb7b33c6e14da6bbaeb089d (patch) | |
| tree | e02ded970acf2fc16242a1cf7596a3dfad27cf94 | |
| parent | 3e5ff04b29807aa32479b90ec43f03d15ebf6061 (diff) | |
| download | riscv-opcodes-b32fad7bb845d5f81cb7b33c6e14da6bbaeb089d.zip riscv-opcodes-b32fad7bb845d5f81cb7b33c6e14da6bbaeb089d.tar.gz riscv-opcodes-b32fad7bb845d5f81cb7b33c6e14da6bbaeb089d.tar.bz2 | |
Some V 0.7.1 updates
| -rw-r--r-- | opcodes-rvv | 27 | ||||
| -rw-r--r-- | opcodes-rvv-pseudo | 10 |
2 files changed, 18 insertions, 19 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index 1523fbe..149fec5 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -84,7 +84,8 @@ vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfmv.s.f 31..26=0x0d 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 -vfmerge.vf 31..26=0x17 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 vfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vford.vf 31..26=0x1a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 @@ -176,9 +177,12 @@ vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vadc.vx 31..26=0x10 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsbc.vx 31..26=0x12 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmerge.vx 31..26=0x17 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vadc.vxm 31..26=0x10 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vxm 31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsbc.vxm 31..26=0x12 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vxm 31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 vseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 @@ -222,9 +226,12 @@ vor.vv 31..26=0x0a vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vxor.vv 31..26=0x0b vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vrgather.vv 31..26=0x0c vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vadc.vv 31..26=0x10 25=1 vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsbc.vv 31..26=0x12 25=1 vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmerge.vv 31..26=0x17 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 +vadc.vvm 31..26=0x10 25=1 vs2 rs1 14..12=0x0 vd 6..0=0x57 +vmadc.vvm 31..26=0x11 25=1 vs2 rs1 14..12=0x0 vd 6..0=0x57 +vsbc.vvm 31..26=0x12 25=1 vs2 rs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vvm 31..26=0x13 25=1 vs2 rs1 14..12=0x0 vd 6..0=0x57 +vmerge.vvm 31..26=0x17 25=0 vs2 rs1 14..12=0x0 vd 6..0=0x57 +vmv.v.v 31..26=0x17 25=1 24..20=0 rs1 14..12=0x0 vd 6..0=0x57 vseq.vv 31..26=0x18 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vsne.vv 31..26=0x19 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vsltu.vv 31..26=0x1a vm vs2 rs1 14..12=0x0 vd 6..0=0x57 @@ -268,8 +275,10 @@ vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vadc.vi 31..26=0x10 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmerge.vi 31..26=0x17 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vadc.vim 31..26=0x10 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vim 31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 vseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 diff --git a/opcodes-rvv-pseudo b/opcodes-rvv-pseudo index 5c31d45..e69de29 100644 --- a/opcodes-rvv-pseudo +++ b/opcodes-rvv-pseudo @@ -1,10 +0,0 @@ -# Split merge instructions into masked and unmasked cases for easier decoding -@vfmerge.masked.vf 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 -@vmerge.masked.vx 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -@vmerge.masked.vv 31..26=0x17 25=0 vs2 rs1 14..12=0x0 vd 6..0=0x57 -@vmerge.masked.vi 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 - -@vfmerge.unmasked.vf 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 -@vmerge.unmasked.vx 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 -@vmerge.unmasked.vv 31..26=0x17 25=1 24..20=0 rs1 14..12=0x0 vd 6..0=0x57 -@vmerge.unmasked.vi 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 |