Add SystemVerilog generation (#24)

2 files changed, 24 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index f6c8825..a685bff 100644
--- a/Makefile
+++ b/Makefile
@@ -20,6 +20,9 @@ inst.chisel: $(ALL_OPCODES) parse-opcodes
 inst.go: opcodes opcodes-pseudo parse-opcodes
 	cat opcodes opcodes-pseudo | ./parse-opcodes -go > $@
 
+inst.sverilog: opcodes opcodes-pseudo parse-opcodes
+	cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-pseudo | ./parse-opcodes -sverilog > $@
+
 instr-table.tex: $(ALL_OPCODES) parse-opcodes
 	cat opcodes opcodes-pseudo | ./parse-opcodes -tex > $@
 
diff --git a/parse-opcodes b/parse-opcodes
index a2c5322..73bbec8 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -889,6 +889,25 @@ def make_chisel():
   print('  }')
   print('}')
 
+def print_sverilog_insn(name):
+  s = "  localparam [31:0] %-18s = 32'b" % name.replace('.', '_').upper()
+  for i in range(31, -1, -1):
+    if yank(mask[name], i, 1):
+      s = '%s%d' % (s, yank(match[name], i, 1))
+    else:
+      s = s + '?'
+  print(s + ";")
+
+def make_sverilog():
+  print('/* Automatically generated by parse-opcodes */')
+  print('package riscv_instr;')
+  for name in namelist:
+    print_sverilog_insn(name)
+  print('  /* CSR Addresses */')
+  for num, name in csrs+csrs32:
+    print('  localparam logic [11:0] CSR_%s = 12\'h%s;' % (name.upper(), hex(num)[2:]))
+  print('endpackage')
+
 def signed(value, width):
   if 0 <= value < (1<<(width-1)):
     return value
@@ -999,6 +1018,8 @@ elif sys.argv[1] == '-privtex':
   make_supervisor_latex_table()
 elif sys.argv[1] == '-chisel':
   make_chisel()
+elif sys.argv[1] == '-sverilog':
+  make_sverilog()
 elif sys.argv[1] == '-c':
   make_c(match,mask)
 elif sys.argv[1] == '-go':