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| author | Andrew Waterman <andrew@sifive.com> | 2019-04-26 11:21:31 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-04-26 11:21:31 -0700 |
| commit | a1a194b98a43129082f07b576597bb55446ead33 (patch) | |
| tree | e0806355ba6b4900508a9725fc765bc4966fd99a | |
| parent | 376c833139c6f230d1eaca8a7028c1e8f55b7976 (diff) | |
| download | riscv-opcodes-a1a194b98a43129082f07b576597bb55446ead33.zip riscv-opcodes-a1a194b98a43129082f07b576597bb55446ead33.tar.gz riscv-opcodes-a1a194b98a43129082f07b576597bb55446ead33.tar.bz2 | |
Create RVQ listing in latex table
| -rwxr-xr-x | parse-opcodes | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/parse-opcodes b/parse-opcodes index 0cdd492..51e442b 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -853,6 +853,22 @@ def make_latex_table(): print_subtitle('RV64D Standard Extension (in addition to RV32D)') print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d') print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x') + print_footer() + + print_header('r','r4','i','s') + print_subtitle('RV32Q Standard Extension') + print_insts('flq', 'fsq') + print_insts('fmadd.q', 'fmsub.q', 'fnmsub.q', 'fnmadd.q') + print_insts('fadd.q', 'fsub.q', 'fmul.q', 'fdiv.q', 'fsqrt.q') + print_insts('fsgnj.q', 'fsgnjn.q', 'fsgnjx.q', 'fmin.q', 'fmax.q') + print_insts('fcvt.s.q', 'fcvt.q.s') + print_insts('fcvt.d.q', 'fcvt.q.d') + print_insts('feq.q', 'flt.q', 'fle.q', 'fclass.q') + print_insts('fcvt.w.q', 'fcvt.wu.q') + print_insts('fcvt.q.w', 'fcvt.q.wu') + print_subtitle('RV64Q Standard Extension (in addition to RV32Q)') + print_insts('fcvt.l.q', 'fcvt.lu.q') + print_insts('fcvt.q.l', 'fcvt.q.lu') print_footer('\\caption{Instruction listing for RISC-V}') def print_chisel_insn(name): |