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| author | Andrew Waterman <andrew@sifive.com> | 2019-05-17 16:04:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-05-17 16:04:57 -0700 |
| commit | 986cf75b071c4a8e580bbe59e2e2d6c436c3de22 (patch) | |
| tree | 9cc33cbca51c6ee71fe6dc7e2fcaefd550730281 | |
| parent | ce6e0aeb01d02cff6ed1eb6d966c85a1c305e4e6 (diff) | |
| download | riscv-opcodes-986cf75b071c4a8e580bbe59e2e2d6c436c3de22.zip riscv-opcodes-986cf75b071c4a8e580bbe59e2e2d6c436c3de22.tar.gz riscv-opcodes-986cf75b071c4a8e580bbe59e2e2d6c436c3de22.tar.bz2 | |
vmv/vext/vfmv are reserved when vm=0
This is not currently stated in the spec, but there is a pull request to
make this explicit: https://github.com/riscv/riscv-v-spec/pull/179
| -rw-r--r-- | opcodes-rvv | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index 2e19ebd..578492c 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -82,7 +82,7 @@ vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmv.s.f 31..26=0x0d vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.s.f 31..26=0x0d 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 vfmerge.vf 31..26=0x17 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 @@ -127,7 +127,7 @@ vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmv.f.s 31..26=0x0c vm vs2 19..15=0 14..12=0x1 rd 6..0=0x57 +vfmv.f.s 31..26=0x0c 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 vfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 @@ -299,7 +299,7 @@ vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vext.x.v 31..26=0x0c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vext.x.v 31..26=0x0c 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 vmpopc.m 31..26=0x14 vm vs2 vs1 14..12=0x2 rd 6..0=0x57 vmfirst.m 31..26=0x15 vm vs2 vs1 14..12=0x2 rd 6..0=0x57 @@ -344,7 +344,7 @@ vwmsacu.vv 31..26=0x3e vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vwmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # OPMVX -vmv.s.x 31..26=0x0d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmv.s.x 31..26=0x0d 25=1 vs2 rs1 14..12=0x6 vd 6..0=0x57 vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 |