diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-13 20:09:28 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 18:23:12 -0700 |
| commit | 73b3d3e819c341d76240365bc7c892fc686795fb (patch) | |
| tree | 4b7b070ce986fbc8911b5d49e44be79f02e934d9 | |
| parent | d8ea6f0401621201503c6f9b259a2ac4cf7b19aa (diff) | |
| download | riscv-opcodes-73b3d3e819c341d76240365bc7c892fc686795fb.zip riscv-opcodes-73b3d3e819c341d76240365bc7c892fc686795fb.tar.gz riscv-opcodes-73b3d3e819c341d76240365bc7c892fc686795fb.tar.bz2 | |
rvv: add vector register field and control register
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rwxr-xr-x | parse-opcodes | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/parse-opcodes b/parse-opcodes index 5140509..1bd628a 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -23,6 +23,7 @@ arglut['fm'] = (31,28) arglut['pred'] = (27,24) arglut['succ'] = (23,20) arglut['rm'] = (14,12) +arglut['funct3'] = (14,12) arglut['imm20'] = (31,12) arglut['jimm20'] = (31,12) arglut['imm12'] = (31,20) @@ -33,7 +34,18 @@ arglut['bimm12lo'] = (11,7) arglut['zimm'] = (19,15) arglut['shamt'] = (25,20) arglut['shamtw'] = (24,20) -arglut['vseglen'] = (31,29) + +# for vectors +arglut['vd'] = (11,7) +arglut['vs3'] = (11,7) +arglut['vs1'] = (19,15) +arglut['vs2'] = (24,20) +arglut['vm'] = (25,25) +arglut['amoop'] = (31,27) +arglut['nf'] = (31,29) +arglut['simm5'] = (19,15) +arglut['zimm11'] = (30,20) + causes = [ (0x00, 'misaligned fetch'), @@ -61,6 +73,9 @@ csrs = [ (0x000, 'ustatus'), (0x004, 'uie'), (0x005, 'utvec'), + (0x008, 'vstart'), + (0x009, 'vxsat'), + (0x00A, 'vxrm'), (0x040, 'uscratch'), (0x041, 'uepc'), (0x042, 'ucause'), @@ -100,6 +115,8 @@ csrs = [ (0xC1D, 'hpmcounter29'), (0xC1E, 'hpmcounter30'), (0xC1F, 'hpmcounter31'), + (0xC20, 'vl'), + (0xC21, 'vtype'), # Standard Supervisor R/W (0x100, 'sstatus'), |