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| author | Andrew Waterman <andrew@sifive.com> | 2019-05-17 15:37:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-05-17 15:58:33 -0700 |
| commit | 71c018432c3494cb75a340b4a3b24fe839c29c21 (patch) | |
| tree | af58c9100869154cab554f5eeda4ce413eb78122 | |
| parent | 61a642421d7f82abf874d56513158d652124f246 (diff) | |
| download | riscv-opcodes-71c018432c3494cb75a340b4a3b24fe839c29c21.zip riscv-opcodes-71c018432c3494cb75a340b4a3b24fe839c29c21.tar.gz riscv-opcodes-71c018432c3494cb75a340b4a3b24fe839c29c21.tar.bz2 | |
Add pseudos for masked/unmasked vmerge to help with decoding
| -rw-r--r-- | Makefile | 4 | ||||
| -rw-r--r-- | opcodes-rvv-pseudo | 10 |
2 files changed, 12 insertions, 2 deletions
@@ -6,7 +6,7 @@ FESVR_H := ../riscv-isa-sim/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv +ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv opcodes-rvv-pseudo install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex @@ -15,7 +15,7 @@ $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse-opcod cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom opcodes-rvv | python ./parse-opcodes -c >> $@ inst.chisel: $(ALL_OPCODES) parse-opcodes - cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-pseudo | ./parse-opcodes -chisel > $@ + cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv opcodes-rvv-pseudo opcodes-pseudo | ./parse-opcodes -chisel > $@ inst.go: opcodes opcodes-pseudo parse-opcodes cat opcodes opcodes-pseudo | ./parse-opcodes -go > $@ diff --git a/opcodes-rvv-pseudo b/opcodes-rvv-pseudo new file mode 100644 index 0000000..5c31d45 --- /dev/null +++ b/opcodes-rvv-pseudo @@ -0,0 +1,10 @@ +# Split merge instructions into masked and unmasked cases for easier decoding +@vfmerge.masked.vf 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 +@vmerge.masked.vx 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +@vmerge.masked.vv 31..26=0x17 25=0 vs2 rs1 14..12=0x0 vd 6..0=0x57 +@vmerge.masked.vi 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 + +@vfmerge.unmasked.vf 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 +@vmerge.unmasked.vx 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 +@vmerge.unmasked.vv 31..26=0x17 25=1 24..20=0 rs1 14..12=0x0 vd 6..0=0x57 +@vmerge.unmasked.vi 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 |