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| author | Andrew Waterman <andrew@sifive.com> | 2019-09-12 14:40:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-09-12 14:40:04 -0700 |
| commit | 442617e61a331fe26108980bad2eacff69b23aaf (patch) | |
| tree | 28b06326db8a11115ebee756b2af41516b1ad5df | |
| parent | a0a75d080afbac61800a9da298f546d6dba93f75 (diff) | |
| download | riscv-opcodes-442617e61a331fe26108980bad2eacff69b23aaf.zip riscv-opcodes-442617e61a331fe26108980bad2eacff69b23aaf.tar.gz riscv-opcodes-442617e61a331fe26108980bad2eacff69b23aaf.tar.bz2 | |
fesvr no longer needs encoding.h
| -rw-r--r-- | Makefile | 5 |
1 files changed, 2 insertions, 3 deletions
@@ -2,15 +2,14 @@ SHELL := /bin/sh ISASIM_H := ../riscv-isa-sim/riscv/encoding.h PK_H := ../riscv-pk/machine/encoding.h -FESVR_H := ../riscv-isa-sim/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv opcodes-rvv-pseudo -install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex +install: $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex -$(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse_opcodes encoding.h +$(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse_opcodes encoding.h cp encoding.h $@ cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom opcodes-rvv | python ./parse_opcodes -c >> $@ |