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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-18 14:44:10 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-18 14:44:35 -0700 |
| commit | 255dd3163e288aa44ee6f0dd71a01facf3300d32 (patch) | |
| tree | a1427072acef9b87082d242ceca7d3ed21cf0c8d | |
| parent | b10e9afcfeacbe34f476ea72281b0bf0938504fe (diff) | |
| download | riscv-opcodes-255dd3163e288aa44ee6f0dd71a01facf3300d32.zip riscv-opcodes-255dd3163e288aa44ee6f0dd71a01facf3300d32.tar.gz riscv-opcodes-255dd3163e288aa44ee6f0dd71a01facf3300d32.tar.bz2 | |
Add pseudos for RV32 shifts with correct immediate constraint
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | opcodes-rvc-pseudo | 5 |
2 files changed, 6 insertions, 1 deletions
@@ -15,7 +15,7 @@ $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse-opcod cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom opcodes-rvv | python ./parse-opcodes -c >> $@ inst.chisel: $(ALL_OPCODES) parse-opcodes - cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv opcodes-rvv-pseudo opcodes-pseudo | ./parse-opcodes -chisel > $@ + cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-rvv opcodes-rvv-pseudo opcodes-pseudo opcodes-pseudo-rvc | ./parse-opcodes -chisel > $@ inst.go: opcodes opcodes-pseudo parse-opcodes cat opcodes opcodes-pseudo | ./parse-opcodes -go > $@ diff --git a/opcodes-rvc-pseudo b/opcodes-rvc-pseudo index a75528b..dd3d929 100644 --- a/opcodes-rvc-pseudo +++ b/opcodes-rvc-pseudo @@ -7,6 +7,11 @@ @c.jalr 1..0=2 15..13=4 12=1 11..7=ignore 6..2=0 @c.ebreak 1..0=2 15..13=4 12=1 11..7=0 6..2=0 +# RV32C +@c.srli.rv32 1..0=1 15..13=4 12=0 11..10=0 9..2=ignore +@c.srai.rv32 1..0=1 15..13=4 12=0 11..10=1 9..2=ignore +@c.slli.rv32 1..0=2 15..13=0 12=0 11..2=ignore + # RV64C @c.ld 1..0=0 15..13=3 12=ignore 11..2=ignore # c.flw for RV32 @c.sd 1..0=0 15..13=7 12=ignore 11..2=ignore # c.fsw for RV32 |