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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-14 16:02:15 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-14 16:02:15 -0800 |
| commit | 03a7a339e7aa82a45c3258124bac82764323e6e3 (patch) | |
| tree | 845748473a3f5ff938236030e9dd3e6ccf9bb059 | |
| parent | cd10c7174835240b86a8ca72ce17aa7422d4970f (diff) | |
| download | riscv-opcodes-03a7a339e7aa82a45c3258124bac82764323e6e3.zip riscv-opcodes-03a7a339e7aa82a45c3258124bac82764323e6e3.tar.gz riscv-opcodes-03a7a339e7aa82a45c3258124bac82764323e6e3.tar.bz2 | |
Don't update binutils' riscv-opc.h automatically anymore
It's upstreamed, so avoid the false impression it can easily change.
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -8,7 +8,7 @@ GAS_H := ../riscv-gnu-toolchain/riscv-binutils-gdb/include/opcode/riscv-opc.h ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom -install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) inst.chisel instr-table.tex priv-instr-table.tex +install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) inst.chisel instr-table.tex priv-instr-table.tex $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes encoding.h cp encoding.h $@ |