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| author | Tsukasa #01 (a4lg) <li@livegrid.org> | 2021-12-14 12:23:59 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-13 19:23:59 -0800 |
| commit | f573c7aec070267b29761af7bf29bff3a51eb4df (patch) | |
| tree | ba12a63bdc922a4cccdd7250576c8fe5de99c623 | |
| parent | 6c34f60fe290613b7ba1d280b29a41179c399e69 (diff) | |
| download | riscv-opcodes-f573c7aec070267b29761af7bf29bff3a51eb4df.zip riscv-opcodes-f573c7aec070267b29761af7bf29bff3a51eb4df.tar.gz riscv-opcodes-f573c7aec070267b29761af7bf29bff3a51eb4df.tar.bz2 | |
Add Zicbo{m,p,z} instructions (#91)
This commit adds instructions defined in RISC-V Base Cache Management
Operation ISA Extensions, version 1.0.0-rc2 (now ratified).
https://github.com/riscv/riscv-CMOs
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | opcodes-zicbo | 12 | ||||
| -rwxr-xr-x | parse_opcodes | 8 |
3 files changed, 21 insertions, 1 deletions
@@ -5,7 +5,7 @@ PK_H := ../riscv-pk/machine/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k +ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k opcodes-zicbo ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv opcodes-rvp ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo diff --git a/opcodes-zicbo b/opcodes-zicbo new file mode 100644 index 0000000..13e1668 --- /dev/null +++ b/opcodes-zicbo @@ -0,0 +1,12 @@ +# Zicbom: cache-block management instructions +cbo.clean rs1 31..20=1 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.flush rs1 31..20=2 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.inval rs1 31..20=0 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicboz: cache-block zero instruction +cbo.zero rs1 31..20=4 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicbop: prefetch hint pseudoinstructions +@prefetch.i rs1 imm12hi 24..20=0 14..12=6 11..7=0 6..2=0x04 1..0=3 +@prefetch.r rs1 imm12hi 24..20=1 14..12=6 11..7=0 6..2=0x04 1..0=3 +@prefetch.w rs1 imm12hi 24..20=3 14..12=6 11..7=0 6..2=0x04 1..0=3 diff --git a/parse_opcodes b/parse_opcodes index ab85d9a..4eb75a1 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -884,6 +884,14 @@ def make_latex_table(): print_insts('amoswap.d') print_insts('amoadd.d', 'amoxor.d', 'amoand.d', 'amoor.d') print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d') + print_subtitle('RV32/RV64 \emph{Zicbom} Standard Extension') + print_insts('cbo.clean') + print_insts('cbo.flush') + print_insts('cbo.inval') + print_subtitle('RV32/RV64 \emph{Zicboz} Standard Extension') + print_insts('cbo.zero') + print_subtitle('RV32/RV64 \emph{Zicbop} Standard Extension') + print_insts('prefetch.i', 'prefetch.r', 'prefetch.w') print_footer() print_header('r','r4','i','s') |