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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-08-03 17:16:52 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-03 14:16:52 -0700 |
| commit | e6f08c19045ac56d8c68445e9c78c57c049d4c66 (patch) | |
| tree | f3194d18754fd4a8f5ff984dd8f548547d56e1aa | |
| parent | a4069bc8ca772c47bf0e12fc758044e5e02b8e8c (diff) | |
| download | riscv-opcodes-e6f08c19045ac56d8c68445e9c78c57c049d4c66.zip riscv-opcodes-e6f08c19045ac56d8c68445e9c78c57c049d4c66.tar.gz riscv-opcodes-e6f08c19045ac56d8c68445e9c78c57c049d4c66.tar.bz2 | |
Fix Svinval rs1 encodings (#78)
| -rw-r--r-- | opcodes-svinval | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/opcodes-svinval b/opcodes-svinval index 502c784..608f32b 100644 --- a/opcodes-svinval +++ b/opcodes-svinval @@ -1,6 +1,6 @@ # Svinval -sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 -sfence.w.inval 11..7=0 rs1 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 -sfence.inval.ir 11..7=0 rs1 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 -hinval.vvma 11..7=0 rs1 rs2 31..25=0x1b 14..12=0 6..2=0x1C 1..0=3 -hinval.gvma 11..7=0 rs1 rs2 31..25=0x3b 14..12=0 6..2=0x1C 1..0=3 +sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 +sfence.w.inval 11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +hinval.vvma 11..7=0 rs1 rs2 31..25=0x1b 14..12=0 6..2=0x1C 1..0=3 +hinval.gvma 11..7=0 rs1 rs2 31..25=0x3b 14..12=0 6..2=0x1C 1..0=3 |