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| author | Andrew Waterman <andrew@sifive.com> | 2022-01-19 20:58:01 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-01-19 20:58:01 -0800 |
| commit | d2b9aeaa4670ccced60887f874a2501bd3dfe0ac (patch) | |
| tree | 0d5ba8a473056f69e4b95ad20db23887f9db3bee | |
| parent | f2f4583551fedeb2b9eb5423f7dd6a7f1ada0696 (diff) | |
| download | riscv-opcodes-d2b9aeaa4670ccced60887f874a2501bd3dfe0ac.zip riscv-opcodes-d2b9aeaa4670ccced60887f874a2501bd3dfe0ac.tar.gz riscv-opcodes-d2b9aeaa4670ccced60887f874a2501bd3dfe0ac.tar.bz2 | |
Fix encodings of HINVAL.VVMA/HINVAL.GVMA
h/t @a4lg
See https://github.com/riscv/riscv-isa-manual/issues/814
| -rw-r--r-- | opcodes-svinval | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes-svinval b/opcodes-svinval index 608f32b..152835b 100644 --- a/opcodes-svinval +++ b/opcodes-svinval @@ -2,5 +2,5 @@ sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 sfence.w.inval 11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 -hinval.vvma 11..7=0 rs1 rs2 31..25=0x1b 14..12=0 6..2=0x1C 1..0=3 -hinval.gvma 11..7=0 rs1 rs2 31..25=0x3b 14..12=0 6..2=0x1C 1..0=3 +hinval.vvma 11..7=0 rs1 rs2 31..25=0x13 14..12=0 6..2=0x1C 1..0=3 +hinval.gvma 11..7=0 rs1 rs2 31..25=0x33 14..12=0 6..2=0x1C 1..0=3 |