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| author | Andrew Waterman <andrew@sifive.com> | 2021-02-24 02:47:30 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-24 02:47:30 -0800 |
| commit | caf888b2141d4fd1eb46925f5de66bfdee524745 (patch) | |
| tree | b52d72fcb2cb01a0127151537ee20e0651b68480 | |
| parent | 03be826f17faedcaee7f60223f402850e254df0a (diff) | |
| parent | e8f03925cc307427dfda0f2f250980fcd3e2d6cf (diff) | |
| download | riscv-opcodes-caf888b2141d4fd1eb46925f5de66bfdee524745.zip riscv-opcodes-caf888b2141d4fd1eb46925f5de66bfdee524745.tar.gz riscv-opcodes-caf888b2141d4fd1eb46925f5de66bfdee524745.tar.bz2 | |
Merge pull request #64 from chihminchao/rvv-v0.10
Rvv v0.10
| -rw-r--r-- | opcodes-rvv | 13 | ||||
| -rwxr-xr-x | parse_opcodes | 1 |
2 files changed, 9 insertions, 5 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index 82b7887..808e6b1 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -4,12 +4,13 @@ # <opcode> is given by specifying one or more range/value pairs: # hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) # -# <args> is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm11 +# <args> is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm10, zimm11 # configuration setting # https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc -vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 -vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 +vsetivli 31=1 30=1 zimm10 zimm 14..12=0x7 rd 6..0=0x57 +vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 +vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 # # Vector Loads and Store @@ -17,6 +18,8 @@ vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 # # Vector Unit-Stride Instructions (including segment part) # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions +vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 @@ -226,8 +229,8 @@ vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 -vfrsqrte7.v 31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57 -vfrece7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 +vfrsqrt7.v 31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57 +vfrec7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 diff --git a/parse_opcodes b/parse_opcodes index 1118e18..6f4ccec 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -46,6 +46,7 @@ arglut['wd'] = (26,26) arglut['amoop'] = (31,27) arglut['nf'] = (31,29) arglut['simm5'] = (19,15) +arglut['zimm10'] = (29,20) arglut['zimm11'] = (30,20) |