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| author | Andrew Waterman <andrew@sifive.com> | 2021-06-20 20:39:56 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-20 20:39:56 -0700 |
| commit | cab0dc75afb09fdf0410aa4d1c5a14088d767cba (patch) | |
| tree | e8f0843850a2584bd29a14e84b636dbea37d1f5e | |
| parent | 944e51610ae3b148786216db6f7ce0c56b31ee72 (diff) | |
| download | riscv-opcodes-cab0dc75afb09fdf0410aa4d1c5a14088d767cba.zip riscv-opcodes-cab0dc75afb09fdf0410aa4d1c5a14088d767cba.tar.gz riscv-opcodes-cab0dc75afb09fdf0410aa4d1c5a14088d767cba.tar.bz2 | |
Move shift instructions to opcodes-rv64i (#68)
The shamt field is 6 bits wide, so doesn't belong in opcodes-rv32i.
The opcodes-pseudo file still contains the RV32 versions with shamtw.
| -rw-r--r-- | opcodes-rv32i | 3 | ||||
| -rw-r--r-- | opcodes-rv64i | 5 |
2 files changed, 5 insertions, 3 deletions
diff --git a/opcodes-rv32i b/opcodes-rv32i index b5490ae..0d008d8 100644 --- a/opcodes-rv32i +++ b/opcodes-rv32i @@ -22,12 +22,9 @@ lui rd imm20 6..2=0x0D 1..0=3 auipc rd imm20 6..2=0x05 1..0=3 addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 -slli rd rs1 31..26=0 shamt 14..12=1 6..2=0x04 1..0=3 slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 -srli rd rs1 31..26=0 shamt 14..12=5 6..2=0x04 1..0=3 -srai rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3 ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 diff --git a/opcodes-rv64i b/opcodes-rv64i index 60a6adc..adced5b 100644 --- a/opcodes-rv64i +++ b/opcodes-rv64i @@ -15,3 +15,8 @@ ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 + +# RV32 versions of these are in opcodes-pseudo +slli rd rs1 31..26=0 shamt 14..12=1 6..2=0x04 1..0=3 +srli rd rs1 31..26=0 shamt 14..12=5 6..2=0x04 1..0=3 +srai rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3 |