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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-22 08:58:39 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-23 22:31:59 -0800 |
| commit | c91a730914c6f7fd351dc80224912db5fae6b4e0 (patch) | |
| tree | 425b2d5a771cf262784dfe7b3182a838af95b52d | |
| parent | 03be826f17faedcaee7f60223f402850e254df0a (diff) | |
| download | riscv-opcodes-c91a730914c6f7fd351dc80224912db5fae6b4e0.zip riscv-opcodes-c91a730914c6f7fd351dc80224912db5fae6b4e0.tar.gz riscv-opcodes-c91a730914c6f7fd351dc80224912db5fae6b4e0.tar.bz2 | |
rvv: add vle1/vse1 instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | opcodes-rvv | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index 82b7887..ac33067 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -17,6 +17,8 @@ vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 # # Vector Unit-Stride Instructions (including segment part) # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions +vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 |