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| author | Tsukasa #01 (a4lg) <research_trasio@irq.a4lg.com> | 2021-12-17 10:18:39 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-16 17:18:39 -0800 |
| commit | b3c1fdc800119eba9e7cf1becbf52cd0e979a9e4 (patch) | |
| tree | 6363b767ac23cbcac1d23d6364fc6c425512101a | |
| parent | a3e0d33be2cb94bd10b89f77c9b04f31331ac2e0 (diff) | |
| download | riscv-opcodes-b3c1fdc800119eba9e7cf1becbf52cd0e979a9e4.zip riscv-opcodes-b3c1fdc800119eba9e7cf1becbf52cd0e979a9e4.tar.gz riscv-opcodes-b3c1fdc800119eba9e7cf1becbf52cd0e979a9e4.tar.bz2 | |
Add new CSR bits defined in Privileged Spec version 1.12 (#94)
| -rw-r--r-- | encoding.h | 31 |
1 files changed, 31 insertions, 0 deletions
@@ -144,6 +144,37 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + +#define HENVCFG_FIOM 0x00000001 +#define HENVCFG_CBIE 0x00000030 +#define HENVCFG_CBCFE 0x00000040 +#define HENVCFG_CBZE 0x00000080 +#define HENVCFG_PBMTE 0x4000000000000000 +#define HENVCFG_STCE 0x8000000000000000 + +#define HENVCFGH_PBMTE 0x40000000 +#define HENVCFGH_STCE 0x80000000 + +#define SENVCFG_FIOM 0x00000001 +#define SENVCFG_CBIE 0x00000030 +#define SENVCFG_CBCFE 0x00000040 +#define SENVCFG_CBZE 0x00000080 + +#define MSECCFG_MML 0x00000001 +#define MSECCFG_MMWP 0x00000002 +#define MSECCFG_RLB 0x00000004 +#define MSECCFG_USEED 0x00000100 +#define MSECCFG_SSEED 0x00000200 + #define PRV_U 0 #define PRV_S 1 #define PRV_M 3 |