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| author | Andrew Waterman <andrew@sifive.com> | 2021-07-28 16:14:30 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-07-28 16:14:30 -0700 |
| commit | a4069bc8ca772c47bf0e12fc758044e5e02b8e8c (patch) | |
| tree | 8a35bc41de778eaeda386934bf8bf9c159e606ad | |
| parent | ec6314c20d507e9277df13233c9364ff5077fa34 (diff) | |
| download | riscv-opcodes-a4069bc8ca772c47bf0e12fc758044e5e02b8e8c.zip riscv-opcodes-a4069bc8ca772c47bf0e12fc758044e5e02b8e8c.tar.gz riscv-opcodes-a4069bc8ca772c47bf0e12fc758044e5e02b8e8c.tar.bz2 | |
Add missing aliases for vle1.v/vse1.v
| -rw-r--r-- | opcodes-rvv-pseudo | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes-rvv-pseudo b/opcodes-rvv-pseudo index 1530ad8..630bb20 100644 --- a/opcodes-rvv-pseudo +++ b/opcodes-rvv-pseudo @@ -6,6 +6,9 @@ @vl4r.v 31..26=3 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 @vl8r.v 31..26=7 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +@vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +@vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 + @vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 @vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 |