diff options
| author | Tsukasa #01 (a4lg) <research_trasio@irq.a4lg.com> | 2021-12-15 20:12:23 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-15 03:12:23 -0800 |
| commit | 922aa58a5f5cb5008db236d9c21375a27197a038 (patch) | |
| tree | 6f75681ce4bb3865c4024f1aebdd33f5a138e636 | |
| parent | 915f9b7e626afd8811b72736aa28df279618c360 (diff) | |
| download | riscv-opcodes-922aa58a5f5cb5008db236d9c21375a27197a038.zip riscv-opcodes-922aa58a5f5cb5008db236d9c21375a27197a038.tar.gz riscv-opcodes-922aa58a5f5cb5008db236d9c21375a27197a038.tar.bz2 | |
Add new CSRs defined in Privileged Spec version 1.12 (again) (#92)
I forgot to add `senvcfg` in the previous PR.
| -rwxr-xr-x | parse_opcodes | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/parse_opcodes b/parse_opcodes index 97fd725..0e77f0c 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -137,6 +137,7 @@ csrs = [ (0x104, 'sie'), (0x105, 'stvec'), (0x106, 'scounteren'), + (0x10A, 'senvcfg'), (0x140, 'sscratch'), (0x141, 'sepc'), (0x142, 'scause'), |