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| author | Zhen Wei <zhen.wei@sifive.com> | 2020-08-04 13:15:00 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-03 22:15:00 -0700 |
| commit | 8d59eaae6d42e5dffa71846eb8296a8a5a461994 (patch) | |
| tree | 2f908d8d073b9eb4f2aa50337d22ba9dab2aefc8 | |
| parent | d688529ff86e477375f82dea3998165ac5538a38 (diff) | |
| download | riscv-opcodes-8d59eaae6d42e5dffa71846eb8296a8a5a461994.zip riscv-opcodes-8d59eaae6d42e5dffa71846eb8296a8a5a461994.tar.gz riscv-opcodes-8d59eaae6d42e5dffa71846eb8296a8a5a461994.tar.bz2 | |
Make *.vv operand naming be consistent with type (#46)
| -rw-r--r-- | opcodes-rvv | 96 |
1 files changed, 48 insertions, 48 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index de894a1..9422373 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -282,54 +282,54 @@ vqmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vqmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # OPIVV -vadd.vv 31..26=0x00 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsub.vv 31..26=0x02 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vminu.vv 31..26=0x04 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmin.vv 31..26=0x05 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmaxu.vv 31..26=0x06 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmax.vv 31..26=0x07 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vand.vv 31..26=0x09 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vor.vv 31..26=0x0a vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vxor.vv 31..26=0x0b vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vrgather.vv 31..26=0x0c vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vrgatherei16.vv 31..26=0x0e vm vs2 rs1 14..12=0x0 vd 6..0=0x57 - -vadc.vvm 31..26=0x10 25=0 vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmadc.vvm 31..26=0x11 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsbc.vvm 31..26=0x12 25=0 vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmsbc.vvm 31..26=0x13 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmerge.vvm 31..26=0x17 25=0 vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmv.v.v 31..26=0x17 25=1 24..20=0 rs1 14..12=0x0 vd 6..0=0x57 -vmseq.vv 31..26=0x18 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmsne.vv 31..26=0x19 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmsltu.vv 31..26=0x1a vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmslt.vv 31..26=0x1b vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmsleu.vv 31..26=0x1c vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vmsle.vv 31..26=0x1d vm vs2 rs1 14..12=0x0 vd 6..0=0x57 - -vsaddu.vv 31..26=0x20 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsadd.vv 31..26=0x21 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vssubu.vv 31..26=0x22 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vssub.vv 31..26=0x23 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsll.vv 31..26=0x25 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsmul.vv 31..26=0x27 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsrl.vv 31..26=0x28 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vsra.vv 31..26=0x29 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vssrl.vv 31..26=0x2a vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vssra.vv 31..26=0x2b vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vnsrl.wv 31..26=0x2c vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vnsra.wv 31..26=0x2d vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vnclipu.wv 31..26=0x2e vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vnclip.wv 31..26=0x2f vm vs2 rs1 14..12=0x0 vd 6..0=0x57 - -vwredsumu.vs 31..26=0x30 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vwredsum.vs 31..26=0x31 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vdotu.vv 31..26=0x38 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vdot.vv 31..26=0x39 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 - -vqmaccu.vv 31..26=0x3c vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vqmacc.vv 31..26=0x3d vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vqmaccsu.vv 31..26=0x3f vm vs2 rs1 14..12=0x0 vd 6..0=0x57 +vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vvm 31..26=0x11 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vvm 31..26=0x13 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 +vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vdotu.vv 31..26=0x38 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vqmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vqmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vqmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # OPIVI vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 |