hyperviosr: add csr mask and interrupt macro name

This part copy the implementation which has been merged in spike

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

6 files changed, 70 insertions, 13 deletions

diff --git a/Makefile b/Makefile
index 4d958c2..d322c44 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@ PK_H := ../riscv-pk/machine/encoding.h
 ENV_H := ../riscv-tests/env/encoding.h
 OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h
 
-ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-system
+ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-system
 ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv
 
 ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo
diff --git a/encoding.h b/encoding.h
index b4fbc16..2e84718 100644
--- a/encoding.h
+++ b/encoding.h
@@ -25,6 +25,8 @@
 #define MSTATUS32_SD        0x80000000
 #define MSTATUS_UXL         0x0000000300000000
 #define MSTATUS_SXL         0x0000000C00000000
+#define MSTATUS_GVA         0x0000004000000000
+#define MSTATUS_MPV         0x0000008000000000
 #define MSTATUS64_SD        0x8000000000000000
 
 #define SSTATUS_UIE         0x00000001
@@ -41,6 +43,21 @@
 #define SSTATUS_UXL         0x0000000300000000
 #define SSTATUS64_SD        0x8000000000000000
 
+#define SSTATUS_VS_MASK     (SSTATUS_SIE | SSTATUS_SPIE | \
+                             SSTATUS_SPP | SSTATUS_SUM | \
+                             SSTATUS_MXR | SSTATUS_UXL)
+
+#define HSTATUS_VSXL        0x300000000
+#define HSTATUS_VTSR        0x00400000
+#define HSTATUS_VTW         0x00200000
+#define HSTATUS_VTVM        0x00100000
+#define HSTATUS_VGEIN       0x0003f000
+#define HSTATUS_HU          0x00000200
+#define HSTATUS_SPVP        0x00000100
+#define HSTATUS_SPV         0x00000080
+#define HSTATUS_GVA         0x00000040
+#define HSTATUS_VSBE        0x00000020
+
 #define USTATUS_UIE         0x00000001
 #define USTATUS_UPIE        0x00000010
 
@@ -102,25 +119,33 @@
 
 #define MIP_USIP            (1 << IRQ_U_SOFT)
 #define MIP_SSIP            (1 << IRQ_S_SOFT)
-#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_VSSIP           (1 << IRQ_VS_SOFT)
 #define MIP_MSIP            (1 << IRQ_M_SOFT)
 #define MIP_UTIP            (1 << IRQ_U_TIMER)
 #define MIP_STIP            (1 << IRQ_S_TIMER)
-#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_VSTIP           (1 << IRQ_VS_TIMER)
 #define MIP_MTIP            (1 << IRQ_M_TIMER)
 #define MIP_UEIP            (1 << IRQ_U_EXT)
 #define MIP_SEIP            (1 << IRQ_S_EXT)
-#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_VSEIP           (1 << IRQ_VS_EXT)
 #define MIP_MEIP            (1 << IRQ_M_EXT)
+#define MIP_SGEIP           (1 << IRQ_S_GEXT)
+
+#define MIP_S_MASK          (MIP_SSIP | MIP_STIP | MIP_SEIP)
+#define MIP_VS_MASK         (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
+#define MIP_HS_MASK         (MIP_VS_MASK | MIP_SGEIP)
+
+#define MIDELEG_FORCED_MASK MIP_HS_MASK
 
 #define SIP_SSIP MIP_SSIP
 #define SIP_STIP MIP_STIP
 
 #define PRV_U 0
 #define PRV_S 1
-#define PRV_H 2
 #define PRV_M 3
 
+#define PRV_HS (PRV_S + 1)
+
 #define SATP32_MODE 0x80000000
 #define SATP32_ASID 0x7FC00000
 #define SATP32_PPN  0x003FFFFF
@@ -135,6 +160,19 @@
 #define SATP_MODE_SV57 10
 #define SATP_MODE_SV64 11
 
+#define HGATP32_MODE 0x80000000
+#define HGATP32_VMID 0x1FC00000
+#define HGATP32_PPN 0x003FFFFF
+
+#define HGATP64_MODE 0xF000000000000000
+#define HGATP64_VMID 0x03FFF00000000000
+#define HGATP64_PPN 0x00000FFFFFFFFFFF
+
+#define HGATP_MODE_OFF 0
+#define HGATP_MODE_SV32X4 1
+#define HGATP_MODE_SV39X4 8
+#define HGATP_MODE_SV48X4 9
+
 #define PMP_R     0x01
 #define PMP_W     0x02
 #define PMP_X     0x04
@@ -148,16 +186,17 @@
 
 #define IRQ_U_SOFT   0
 #define IRQ_S_SOFT   1
-#define IRQ_H_SOFT   2
+#define IRQ_VS_SOFT  2
 #define IRQ_M_SOFT   3
 #define IRQ_U_TIMER  4
 #define IRQ_S_TIMER  5
-#define IRQ_H_TIMER  6
+#define IRQ_VS_TIMER 6
 #define IRQ_M_TIMER  7
 #define IRQ_U_EXT    8
 #define IRQ_S_EXT    9
-#define IRQ_H_EXT    10
+#define IRQ_VS_EXT   10
 #define IRQ_M_EXT    11
+#define IRQ_S_GEXT   12
 #define IRQ_COP      12
 #define IRQ_HOST     13
 
diff --git a/opcodes-rv32h b/opcodes-rv32h
new file mode 100644
index 0000000..84a361d
--- /dev/null
+++ b/opcodes-rv32h
@@ -0,0 +1,14 @@
+# Hypervisor extension
+hfence.vvma 11..7=0 rs1        rs2 31..25=0x11  14..12=0 6..2=0x1C 1..0=3
+hfence.gvma 11..7=0 rs1        rs2 31..25=0x31  14..12=0 6..2=0x1C 1..0=3
+
+hlv.b            rd rs1 24..20=0x0 31..25=0x30  14..12=4 6..2=0x1C 1..0=3
+hlv.bu           rd rs1 24..20=0x1 31..25=0x30  14..12=4 6..2=0x1C 1..0=3
+hlv.h            rd rs1 24..20=0x0 31..25=0x32  14..12=4 6..2=0x1C 1..0=3
+hlv.hu           rd rs1 24..20=0x1 31..25=0x32  14..12=4 6..2=0x1C 1..0=3
+hlvx.hu          rd rs1 24..20=0x3 31..25=0x32  14..12=4 6..2=0x1C 1..0=3
+hlv.w            rd rs1 24..20=0x0 31..25=0x34  14..12=4 6..2=0x1C 1..0=3
+hlvx.wu          rd rs1 24..20=0x3 31..25=0x34  14..12=4 6..2=0x1C 1..0=3
+hsv.b       11..7=0 rs1        rs2 31..25=0x31  14..12=4 6..2=0x1C 1..0=3
+hsv.h       11..7=0 rs1        rs2 31..25=0x33  14..12=4 6..2=0x1C 1..0=3
+hsv.w       11..7=0 rs1        rs2 31..25=0x35  14..12=4 6..2=0x1C 1..0=3
diff --git a/opcodes-rv64h b/opcodes-rv64h
new file mode 100644
index 0000000..75589e1
--- /dev/null
+++ b/opcodes-rv64h
@@ -0,0 +1,4 @@
+# Hypervisor extension
+hlv.wu           rd rs1 24..20=0x1 31..25=0x34  14..12=4 6..2=0x1C 1..0=3
+hlv.d            rd rs1 24..20=0x0 31..25=0x36  14..12=4 6..2=0x1C 1..0=3
+hsv.d       11..7=0 rs1        rs2 31..25=0x37  14..12=4 6..2=0x1C 1..0=3
diff --git a/opcodes-system b/opcodes-system
index 52013d7..9517814 100644
--- a/opcodes-system
+++ b/opcodes-system
@@ -13,7 +13,3 @@ csrrc     rd      rs1      imm12        14..12=3 6..2=0x1C 1..0=3
 csrrwi    rd      rs1      imm12        14..12=5 6..2=0x1C 1..0=3
 csrrsi    rd      rs1      imm12        14..12=6 6..2=0x1C 1..0=3
 csrrci    rd      rs1      imm12        14..12=7 6..2=0x1C 1..0=3
-
-# Hypervisor extension
-hfence.vvma 11..7=0 rs1 rs2 31..25=0x11  14..12=0 6..2=0x1C 1..0=3
-hfence.gvma 11..7=0 rs1 rs2 31..25=0x31  14..12=0 6..2=0x1C 1..0=3
diff --git a/parse_opcodes b/parse_opcodes
index 4fd7489..56833be 100755
--- a/parse_opcodes
+++ b/parse_opcodes
@@ -60,11 +60,15 @@ causes = [
   (0x07, 'store access'),
   (0x08, 'user_ecall'),
   (0x09, 'supervisor_ecall'),
-  (0x0A, 'hypervisor_ecall'),
+  (0x0A, 'virtual_supervisor_ecall'),
   (0x0B, 'machine_ecall'),
   (0x0C, 'fetch page fault'),
   (0x0D, 'load page fault'),
   (0x0F, 'store page fault'),
+  (0x14, 'fetch guest page fault'),
+  (0x15, 'load guest page fault'),
+  (0x16, 'virtual instruction'),
+  (0x17, 'store guest page fault'),
 ]
 
 csrs = [