diff options
| author | Daniel Lustig <dlustig@nvidia.com> | 2021-07-19 19:15:58 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-19 16:15:58 -0700 |
| commit | 65af4131c26fb4743fee4c4efbdff8a59eb4e48a (patch) | |
| tree | 2a74f0d7e94ae3af3a63f2d3d0d5cd466af49385 | |
| parent | e46f324eec2f783803fa776f589b9ef047db3af7 (diff) | |
| download | riscv-opcodes-65af4131c26fb4743fee4c4efbdff8a59eb4e48a.zip riscv-opcodes-65af4131c26fb4743fee4c4efbdff8a59eb4e48a.tar.gz riscv-opcodes-65af4131c26fb4743fee4c4efbdff8a59eb4e48a.tar.bz2 | |
Virtual memory updates (#76)
* Add Svinval instructions
* Add PTE defines for Priv 1.12 and Svpbmt
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | encoding.h | 3 | ||||
| -rw-r--r-- | opcodes-svinval | 6 | ||||
| -rwxr-xr-x | parse_opcodes | 6 |
4 files changed, 16 insertions, 1 deletions
@@ -5,7 +5,7 @@ PK_H := ../riscv-pk/machine/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k +ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo @@ -216,7 +216,10 @@ #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ #define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ #define PTE_PPN_SHIFT 10 diff --git a/opcodes-svinval b/opcodes-svinval new file mode 100644 index 0000000..502c784 --- /dev/null +++ b/opcodes-svinval @@ -0,0 +1,6 @@ +# Svinval +sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 +sfence.w.inval 11..7=0 rs1 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +sfence.inval.ir 11..7=0 rs1 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +hinval.vvma 11..7=0 rs1 rs2 31..25=0x1b 14..12=0 6..2=0x1C 1..0=3 +hinval.gvma 11..7=0 rs1 rs2 31..25=0x3b 14..12=0 6..2=0x1C 1..0=3 diff --git a/parse_opcodes b/parse_opcodes index 28c4f05..7bb4dc9 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -893,6 +893,12 @@ def make_supervisor_latex_table(): print_subtitle('Hypervisor Memory-Management Instructions') print_insts('hfence.vvma') print_insts('hfence.gvma') + print_subtitle('Svinval Memory-Management Instructions') + print_insts('sinval.vma') + print_insts('sfence.w.inval') + print_insts('sfence.inval.ir') + print_insts('hinval.vvma') + print_insts('hinval.gvma') print_footer('\\caption{RISC-V Privileged Instructions}') def make_latex_table(): |