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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-11-02 12:03:54 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-11-02 12:09:01 -0700 |
| commit | 53fbda5873ec5ffdfd7dd62cd5961fe99c6299a2 (patch) | |
| tree | c470da9abdbf61d42c1f13af8196e2e7184fea39 | |
| parent | 7cdc0412849acbd5a4a041b24c9defb7e2f6d9bc (diff) | |
| download | riscv-opcodes-53fbda5873ec5ffdfd7dd62cd5961fe99c6299a2.zip riscv-opcodes-53fbda5873ec5ffdfd7dd62cd5961fe99c6299a2.tar.gz riscv-opcodes-53fbda5873ec5ffdfd7dd62cd5961fe99c6299a2.tar.bz2 | |
Add new hypervisor bits to mstatush
In Spike, I added these by hand in
https://github.com/riscv-software-src/riscv-isa-sim/commit/4730be82e63ec8bf4a30aa59afee5e5b58a0fbe4
| -rw-r--r-- | encoding.h | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -33,6 +33,8 @@ #define MSTATUSH_SBE 0x00000010 #define MSTATUSH_MBE 0x00000020 +#define MSTATUSH_GVA 0x00000040 +#define MSTATUSH_MPV 0x00000080 #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 |