Clean up handling of bitmanip extensions

There's no such thing as "B", which continues to be a source of
confusion.  Time to fix that.

cc @ben-marshall since I added Zbkb/Zbkx.

Resolves #101

13 files changed, 120 insertions, 92 deletions

diff --git a/Makefile b/Makefile
index 5a03913..6de8704 100644
--- a/Makefile
+++ b/Makefile
@@ -6,7 +6,7 @@ ENV_H := ../riscv-tests/env/encoding.h
 OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h
 INSTALL_HEADER_FILES := $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H)
 
-ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k opcodes-zicbo
+ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32xbitmanip opcodes-rv64xbitmanip opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k opcodes-zicbo opcodes-rv32zba opcodes-rv32zbb opcodes-rv32zbc opcodes-rv32zbkb opcodes-rv32zbkx opcodes-rv32zbs opcodes-rv64zba opcodes-rv64zbb opcodes-rv64zbkb
 ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv opcodes-rvp
 
 ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo
diff --git a/opcodes-rv32b b/opcodes-rv32b
deleted file mode 100644
index 1099c1d..0000000
--- a/opcodes-rv32b
+++ /dev/null
@@ -1,74 +0,0 @@
-andn       rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3
-orn        rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3
-xnor       rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3
-
-slo        rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3
-sro        rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3
-rol        rd rs1 rs2 31..25=48 14..12=1 6..2=0x0C 1..0=3
-ror        rd rs1 rs2 31..25=48 14..12=5 6..2=0x0C 1..0=3
-
-bclr       rd rs1 rs2 31..25=36 14..12=1 6..2=0x0C 1..0=3
-bset       rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3
-binv       rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3
-bext       rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3
-gorc       rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3
-grev       rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3
-
-sloi       rd rs1 31..26=8  shamt 14..12=1 6..2=0x04 1..0=3
-sroi       rd rs1 31..26=8  shamt 14..12=5 6..2=0x04 1..0=3
-rori       rd rs1 31..26=24 shamt 14..12=5 6..2=0x04 1..0=3
-
-bclri      rd rs1 31..26=18 shamt 14..12=1 6..2=0x04 1..0=3
-bseti      rd rs1 31..26=10 shamt 14..12=1 6..2=0x04 1..0=3
-binvi      rd rs1 31..26=26 shamt 14..12=1 6..2=0x04 1..0=3
-bexti      rd rs1 31..26=18 shamt 14..12=5 6..2=0x04 1..0=3
-gorci      rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3
-grevi      rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3
-
-cmix       rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3
-cmov       rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3
-
-fsl        rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3
-fsr        rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3
-fsri       rd rs1 shamt rs3   26=1 14..12=5 6..2=0x04 1..0=3
-
-clz        rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3
-ctz        rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3
-cpop       rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3
-sext.b     rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3
-sext.h     rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3
-
-crc32.b    rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3
-crc32.h    rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3
-crc32.w    rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3
-crc32c.b   rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3
-crc32c.h   rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3
-crc32c.w   rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3
-
-sh1add     rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3
-sh2add     rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3
-sh3add     rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3
-
-clmul      rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3
-clmulr     rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3
-clmulh     rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3
-min        rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3
-minu       rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3
-max        rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3
-maxu       rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3
-
-shfl       rd rs1 rs2 31..25=4  14..12=1 6..2=0x0C 1..0=3
-unshfl     rd rs1 rs2 31..25=4  14..12=5 6..2=0x0C 1..0=3
-bcompress  rd rs1 rs2 31..25=4  14..12=6 6..2=0x0C 1..0=3
-bdecompress rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3
-pack       rd rs1 rs2 31..25=4  14..12=4 6..2=0x0C 1..0=3
-packu      rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3
-packh      rd rs1 rs2 31..25=4  14..12=7 6..2=0x0C 1..0=3
-bfp        rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3
-
-shfli      rd rs1 31..25=4 shamtw 14..12=1 6..2=0x04 1..0=3
-unshfli    rd rs1 31..25=4 shamtw 14..12=5 6..2=0x04 1..0=3
-
-xperm4     rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3
-xperm8     rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3
-xperm16    rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3
diff --git a/opcodes-rv32xbitmanip b/opcodes-rv32xbitmanip
new file mode 100644
index 0000000..173fb8c
--- /dev/null
+++ b/opcodes-rv32xbitmanip
@@ -0,0 +1,42 @@
+# This file contains unratified instructions that have been proposed
+# by the Bit Manipulation TG but have not been ratified.  (Spike
+# supports them via the Xbitmanip extension, hence the filename.)
+
+slo        rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3
+sro        rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3
+
+gorc       rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3
+grev       rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3
+
+sloi       rd rs1 31..26=8  shamt 14..12=1 6..2=0x04 1..0=3
+sroi       rd rs1 31..26=8  shamt 14..12=5 6..2=0x04 1..0=3
+
+# These are marked as pseudos to avoid conflicting with orc.b and rev8
+@gorci     rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3
+@grevi     rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3
+
+cmix       rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3
+cmov       rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3
+
+fsl        rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3
+fsr        rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3
+fsri       rd rs1 shamt rs3   26=1 14..12=5 6..2=0x04 1..0=3
+
+crc32.b    rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3
+crc32.h    rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3
+crc32.w    rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3
+crc32c.b   rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3
+crc32c.h   rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3
+crc32c.w   rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3
+
+shfl       rd rs1 rs2 31..25=4  14..12=1 6..2=0x0C 1..0=3
+unshfl     rd rs1 rs2 31..25=4  14..12=5 6..2=0x0C 1..0=3
+bcompress  rd rs1 rs2 31..25=4  14..12=6 6..2=0x0C 1..0=3
+bdecompress rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3
+packu      rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3
+bfp        rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3
+
+shfli      rd rs1 31..25=4 shamtw 14..12=1 6..2=0x04 1..0=3
+unshfli    rd rs1 31..25=4 shamtw 14..12=5 6..2=0x04 1..0=3
+
+xperm16    rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3
diff --git a/opcodes-rv32zba b/opcodes-rv32zba
new file mode 100644
index 0000000..65eb420
--- /dev/null
+++ b/opcodes-rv32zba
@@ -0,0 +1,3 @@
+sh1add     rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3
+sh2add     rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3
+sh3add     rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3
diff --git a/opcodes-rv32zbb b/opcodes-rv32zbb
new file mode 100644
index 0000000..ed80dfe
--- /dev/null
+++ b/opcodes-rv32zbb
@@ -0,0 +1,24 @@
+andn       rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3
+orn        rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3
+xnor       rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3
+
+rol        rd rs1 rs2 31..25=48 14..12=1 6..2=0x0C 1..0=3
+ror        rd rs1 rs2 31..25=48 14..12=5 6..2=0x0C 1..0=3
+
+rori       rd rs1 31..26=24 shamt 14..12=5 6..2=0x04 1..0=3
+
+clz        rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3
+ctz        rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3
+cpop       rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3
+sext.b     rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3
+sext.h     rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3
+
+min        rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3
+minu       rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3
+max        rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3
+maxu       rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3
+
+orc.b      rd rs1 31..26=10 25..20=7 14..12=5 6..2=0x04 1..0=3
+
+@rev8.rv32   rd rs1 31..26=26 25..20=24 14..12=5 6..2=0x04 1..0=3
+@zext.h.rv32 rd rs1 31..25=4  24..20=0  14..12=4 6..2=0x0C 1..0=3
diff --git a/opcodes-rv32zbc b/opcodes-rv32zbc
new file mode 100644
index 0000000..821518b
--- /dev/null
+++ b/opcodes-rv32zbc
@@ -0,0 +1,3 @@
+clmul      rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3
+clmulr     rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3
+clmulh     rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3
diff --git a/opcodes-rv32zbkb b/opcodes-rv32zbkb
new file mode 100644
index 0000000..5c9e2d5
--- /dev/null
+++ b/opcodes-rv32zbkb
@@ -0,0 +1,8 @@
+# This file includes only the RV32Zbkb instructions that are not in RV32Zbb
+
+pack       rd rs1 rs2 31..25=4  14..12=4 6..2=0x0C 1..0=3
+packh      rd rs1 rs2 31..25=4  14..12=7 6..2=0x0C 1..0=3
+
+brev8      rd rs1 31..26=26 25..20=7  14..12=5 6..2=0x04 1..0=3
+unzip      rd rs1 31..25=4  24..20=15 14..12=5 6..2=0x04 1..0=3
+zip        rd rs1 31..25=4  24..20=15 14..12=1 6..2=0x04 1..0=3
diff --git a/opcodes-rv32zbkx b/opcodes-rv32zbkx
new file mode 100644
index 0000000..12bc0b4
--- /dev/null
+++ b/opcodes-rv32zbkx
@@ -0,0 +1,2 @@
+xperm4     rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3
+xperm8     rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3
diff --git a/opcodes-rv32zbs b/opcodes-rv32zbs
new file mode 100644
index 0000000..1de3fc2
--- /dev/null
+++ b/opcodes-rv32zbs
@@ -0,0 +1,9 @@
+bclr       rd rs1 rs2 31..25=36 14..12=1 6..2=0x0C 1..0=3
+bset       rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3
+binv       rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3
+bext       rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3
+
+bclri      rd rs1 31..26=18 shamt 14..12=1 6..2=0x04 1..0=3
+bseti      rd rs1 31..26=10 shamt 14..12=1 6..2=0x04 1..0=3
+binvi      rd rs1 31..26=26 shamt 14..12=1 6..2=0x04 1..0=3
+bexti      rd rs1 31..26=18 shamt 14..12=5 6..2=0x04 1..0=3
diff --git a/opcodes-rv64b b/opcodes-rv64xbitmanip
index 705d993..6e6a595 100644
--- a/opcodes-rv64b
+++ b/opcodes-rv64xbitmanip
@@ -1,4 +1,6 @@
-# RV64B additions to RV32B
+# This file contains unratified instructions that have been proposed
+# by the Bit Manipulation TG but have not been ratified.  (Spike
+# supports them via the Xbitmanip extension, hence the filename.)
 
 bmatflip   rd rs1 31..20=0x603 14..12=1 6..2=0x04 1..0=3
 crc32.d    rd rs1 31..20=0x613 14..12=1 6..2=0x04 1..0=3
@@ -7,21 +9,14 @@ crc32c.d   rd rs1 31..20=0x61B 14..12=1 6..2=0x04 1..0=3
 bmator     rd rs1 rs2 31..25=4  14..12=3 6..2=0x0C 1..0=3
 bmatxor    rd rs1 rs2 31..25=36 14..12=3 6..2=0x0C 1..0=3
 
-slli.uw    rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3
-
-add.uw     rd rs1 rs2 31..25=4  14..12=0 6..2=0x0E 1..0=3
-
 slow       rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3
 srow       rd rs1 rs2 31..25=16 14..12=5 6..2=0x0E 1..0=3
-rolw       rd rs1 rs2 31..25=48 14..12=1 6..2=0x0E 1..0=3
-rorw       rd rs1 rs2 31..25=48 14..12=5 6..2=0x0E 1..0=3
 
 gorcw      rd rs1 rs2 31..25=20 14..12=5 6..2=0x0E 1..0=3
 grevw      rd rs1 rs2 31..25=52 14..12=5 6..2=0x0E 1..0=3
 
 sloiw      rd rs1 31..26=8  25=0 shamtw 14..12=1 6..2=0x06 1..0=3
 sroiw      rd rs1 31..26=8  25=0 shamtw 14..12=5 6..2=0x06 1..0=3
-roriw      rd rs1 31..26=24 25=0 shamtw 14..12=5 6..2=0x06 1..0=3
 
 gorciw     rd rs1 31..26=10 25=0 shamtw 14..12=5 6..2=0x06 1..0=3
 greviw     rd rs1 31..26=26 25=0 shamtw 14..12=5 6..2=0x06 1..0=3
@@ -30,19 +25,10 @@ fslw       rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0E 1..0=3
 fsrw       rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0E 1..0=3
 fsriw      rd rs1 shamtw rs3 26..25=2 14..12=5 6..2=0x06 1..0=3
 
-clzw       rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3
-ctzw       rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3
-cpopw      rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3
-
-sh1add.uw  rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3
-sh2add.uw  rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3
-sh3add.uw  rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3
-
 shflw      rd rs1 rs2 31..25=4  14..12=1 6..2=0x0E 1..0=3
 unshflw    rd rs1 rs2 31..25=4  14..12=5 6..2=0x0E 1..0=3
 bcompressw rd rs1 rs2 31..25=4  14..12=6 6..2=0x0E 1..0=3
 bdecompressw rd rs1 rs2 31..25=36 14..12=6 6..2=0x0E 1..0=3
-packw      rd rs1 rs2 31..25=4  14..12=4 6..2=0x0E 1..0=3
 packuw     rd rs1 rs2 31..25=36 14..12=4 6..2=0x0E 1..0=3
 bfpw       rd rs1 rs2 31..25=36 14..12=7 6..2=0x0E 1..0=3
 
diff --git a/opcodes-rv64zba b/opcodes-rv64zba
new file mode 100644
index 0000000..28a1cfc
--- /dev/null
+++ b/opcodes-rv64zba
@@ -0,0 +1,9 @@
+# RV64Zba additions to RV32Zba
+
+slli.uw    rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3
+
+add.uw     rd rs1 rs2 31..25=4  14..12=0 6..2=0x0E 1..0=3
+
+sh1add.uw  rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3
+sh2add.uw  rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3
+sh3add.uw  rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3
diff --git a/opcodes-rv64zbb b/opcodes-rv64zbb
new file mode 100644
index 0000000..c2ab552
--- /dev/null
+++ b/opcodes-rv64zbb
@@ -0,0 +1,13 @@
+# RV64Zbb additions to RV32Zbb
+
+rolw       rd rs1 rs2 31..25=48 14..12=1 6..2=0x0E 1..0=3
+rorw       rd rs1 rs2 31..25=48 14..12=5 6..2=0x0E 1..0=3
+
+roriw      rd rs1 31..26=24 25=0 shamtw 14..12=5 6..2=0x06 1..0=3
+
+clzw       rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3
+ctzw       rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3
+cpopw      rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3
+
+rev8       rd rs1 31..26=26 25..20=56 14..12=5 6..2=0x04 1..0=3
+@zext.h    rd rs1 31..25=4  24..20=0  14..12=4 6..2=0x0E 1..0=3
diff --git a/opcodes-rv64zbkb b/opcodes-rv64zbkb
new file mode 100644
index 0000000..1c3146d
--- /dev/null
+++ b/opcodes-rv64zbkb
@@ -0,0 +1,3 @@
+# This file includes only the RV64Zbkb instructions that are not in RV64Zbb
+
+packw      rd rs1 rs2 31..25=4  14..12=4 6..2=0x0E 1..0=3