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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-10 00:43:27 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-10 00:43:27 -0800 |
| commit | fee20f1c9002a67c7fce73d483f59a6804219ab2 (patch) | |
| tree | c124e2c196b24916a3f5d78cc6d4e9822fcc9020 | |
| parent | b4125c052451f82a0182f0de8bb3f9f671fc55c9 (diff) | |
| download | riscv-opcodes-fee20f1c9002a67c7fce73d483f59a6804219ab2.zip riscv-opcodes-fee20f1c9002a67c7fce73d483f59a6804219ab2.tar.gz riscv-opcodes-fee20f1c9002a67c7fce73d483f59a6804219ab2.tar.bz2 | |
Allow immediates for write_csr; check for signedness
| -rw-r--r-- | encoding.h | 18 |
1 files changed, 12 insertions, 6 deletions
@@ -132,22 +132,28 @@ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) -#define write_csr(reg, val) \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)) +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) -#define swap_csr(reg, val) ({ long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ __tmp; }) #define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (bit) < 32) \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ __tmp; }) #define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (bit) < 32) \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ |