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| author | Tim Newsome <tim@sifive.com> | 2016-08-25 13:53:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-25 13:53:21 -0700 |
| commit | 1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658 (patch) | |
| tree | f490e34e1620de350827781653085b7daa9be431 | |
| parent | 16c63f381f1e5318fa3edcff9facb7166332a151 (diff) | |
| download | riscv-opcodes-1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658.zip riscv-opcodes-1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658.tar.gz riscv-opcodes-1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658.tar.bz2 | |
Make hardware triggers match latest spec.
| -rw-r--r-- | encoding.h | 48 | ||||
| -rwxr-xr-x | parse-opcodes | 8 |
2 files changed, 34 insertions, 22 deletions
@@ -37,7 +37,6 @@ #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET (1<<29) #define DCSR_FULLRESET (1<<28) -#define DCSR_HWBPCOUNT (0xfff<<16) #define DCSR_EBREAKM (1<<15) #define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKS (1<<13) @@ -57,6 +56,36 @@ #define DCSR_CAUSE_STEP 4 #define DCSR_CAUSE_HALT 5 +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + #define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) @@ -101,23 +130,6 @@ #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 -// breakpoint control fields -#define BPCONTROL_X 0x00000001 -#define BPCONTROL_W 0x00000002 -#define BPCONTROL_R 0x00000004 -#define BPCONTROL_U 0x00000008 -#define BPCONTROL_S 0x00000010 -#define BPCONTROL_H 0x00000020 -#define BPCONTROL_M 0x00000040 -#define BPCONTROL_BPMATCH 0x00000780 -#ifdef __riscv64 -# define BPCONTROL_BPAMASKMAX 0x0F80000000000000 -# define BPCONTROL_TDRTYPE 0xF000000000000000 -#else -# define BPCONTROL_BPAMASKMAX 0x0F800000 -# define BPCONTROL_TDRTYPE 0xF0000000 -#endif - // page table entry (PTE) fields #define PTE_V 0x001 // Valid #define PTE_R 0x002 // Read diff --git a/parse-opcodes b/parse-opcodes index 44a22da..ba32f6a 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -92,10 +92,10 @@ csrs = [ (0x704, 'mscycle_delta'), (0x705, 'mstime_delta'), (0x706, 'msinstret_delta'), - (0x7a0, 'tdrselect'), - (0x7a1, 'tdrdata1'), - (0x7a2, 'tdrdata2'), - (0x7a3, 'tdrdata3'), + (0x7a0, 'tselect'), + (0x7a1, 'tdata0'), + (0x7a2, 'tdata1'), + (0x7a3, 'tdata2'), (0x7b0, 'dcsr'), (0x7b1, 'dpc'), (0x7b2, 'dscratch'), |