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authorAndrew Waterman <waterman@cs.berkeley.edu>2015-09-08 16:47:04 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2015-09-08 16:47:04 -0700
commit17997b79bb9fc98a0d3465db4f883f3793725bbd (patch)
tree2957dfc09b6c876afc111214f20d4c6fb174e191
parent04056f9087e131a8c46167ce5f257abd73c2c137 (diff)
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update to latest RVC proposal
-rw-r--r--.gitignore1
-rw-r--r--Makefile4
-rw-r--r--opcodes-rvc39
-rw-r--r--opcodes-rvc-pseudo36
-rwxr-xr-xparse-opcodes7
5 files changed, 35 insertions, 52 deletions
diff --git a/.gitignore b/.gitignore
index 72c1533..5b578f1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,4 @@
.*.swp
inst.chisel
instr-table.tex
+priv-instr-table.tex
diff --git a/Makefile b/Makefile
index b5457f6..aadf291 100644
--- a/Makefile
+++ b/Makefile
@@ -8,13 +8,13 @@ ENV_H := ../riscv-tests/env/encoding.h
GAS_H := ../riscv-gnu-toolchain/binutils/include/opcode/riscv-opc.h
XCC_H := ../riscv-gnu-toolchain/gcc/gcc/config/riscv/riscv-opc.h
-ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-rvc-pseudo opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom
+ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-hwacha-pseudo opcodes-hwacha opcodes-hwacha-ut opcodes-custom
install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex priv-instr-table.tex
$(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes encoding.h
cp encoding.h $@
- cat opcodes opcodes-rvc | ./parse-opcodes -c >> $@
+ cat opcodes opcodes-rvc opcodes-rvc-pseudo | ./parse-opcodes -c >> $@
$(GAS_H) $(XCC_H): $(ALL_OPCODES) parse-opcodes
cat $(ALL_OPCODES) | ./parse-opcodes -c > $@
diff --git a/opcodes-rvc b/opcodes-rvc
index 36dcdd4..5f18a8e 100644
--- a/opcodes-rvc
+++ b/opcodes-rvc
@@ -1,37 +1,32 @@
# compressed instructions
# C0 encoding space
-c.mv 1..0=0 15..13=0 12=0 11..2=ignore
-c.add 1..0=0 15..13=0 12=1 11..2=ignore # c.ebreak when rd=0, rs2=0
-c.srai 1..0=0 15..13=1 12=ignore 11..2=ignore
-c.sw 1..0=0 15..13=2 12=ignore 11..2=ignore
-c.sd 1..0=0 15..13=3 12=ignore 11..2=ignore
-c.sub 1..0=0 15..13=4 12=0 11..2=ignore
-c.addw 1..0=0 15..13=4 12=1 11..2=ignore
-c.add3 1..0=0 15..13=5 12..7=ignore 6..5=0 4..2=ignore
-c.sub3 1..0=0 15..13=5 12..7=ignore 6..5=1 4..2=ignore
-c.or3 1..0=0 15..13=5 12..7=ignore 6..5=2 4..2=ignore
-c.and3 1..0=0 15..13=5 12..7=ignore 6..5=3 4..2=ignore
-c.lw 1..0=0 15..13=6 12=ignore 11..2=ignore
-c.ld 1..0=0 15..13=7 12=ignore 11..2=ignore
-
+c.mv 1..0=0 15..13=0 12=0 11..2=ignore # !rs2 = c.jr
+c.add 1..0=0 15..13=0 12=1 11..2=ignore # !rs1 = c.ebreak; !rs2=c.jalr
+c.fsd 1..0=0 15..13=1 12=ignore 11..2=ignore
+c.sw 1..0=0 15..13=2 12=ignore 11..2=ignore
+c.fsw 1..0=0 15..13=3 12=ignore 11..2=ignore # c.sd for RV64
+c.addi4spn 1..0=0 15..13=4 12=ignore 11..2=ignore
+c.fld 1..0=0 15..13=5 12=ignore 11..2=ignore
+c.lw 1..0=0 15..13=6 12=ignore 11..2=ignore
+c.flw 1..0=0 15..13=7 12=ignore 11..2=ignore # c.ld for RV64
# C1 encoding space
c.slli 1..0=1 15..13=0 12=ignore 11..2=ignore
-c.srli 1..0=1 15..13=1 12=ignore 11..2=ignore
+c.fsdsp 1..0=1 15..13=1 12=ignore 11..2=ignore
c.swsp 1..0=1 15..13=2 12=ignore 11..2=ignore
-c.sdsp 1..0=1 15..13=3 12=ignore 11..2=ignore
-c.slliw 1..0=1 15..13=4 12=ignore 11..2=ignore
-c.addi4spn 1..0=1 15..13=5 12=ignore 11..2=ignore
+c.fswsp 1..0=1 15..13=3 12=ignore 11..2=ignore # c.sdsp for RV64
+c.addw 1..0=1 15..13=4 12=0 11..2=ignore
+c.fldsp 1..0=1 15..13=5 12=ignore 11..2=ignore
c.lwsp 1..0=1 15..13=6 12=ignore 11..2=ignore
-c.ldsp 1..0=1 15..13=7 12=ignore 11..2=ignore
+c.flwsp 1..0=1 15..13=7 12=ignore 11..2=ignore # c.ldsp for RV64
# C2 encoding space
c.j 1..0=2 15..13=0 12=ignore 11..2=ignore
c.jal 1..0=2 15..13=1 12=ignore 11..2=ignore
c.beqz 1..0=2 15..13=2 12=ignore 11..2=ignore
c.bnez 1..0=2 15..13=3 12=ignore 11..2=ignore
-c.li 1..0=2 15..13=4 12=ignore 11..2=ignore # c.jr when simm=0
-c.lui 1..0=2 15..13=5 12=ignore 11..2=ignore # c.jalr when simm=0
-c.addi 1..0=2 15..13=6 12=ignore 11..2=ignore # c.addi16sp when rd=0
+c.li 1..0=2 15..13=4 12=ignore 11..2=ignore
+c.lui 1..0=2 15..13=5 12=ignore 11..2=ignore # c.addi16sp when rd=0
+c.addi 1..0=2 15..13=6 12=ignore 11..2=ignore
c.addiw 1..0=2 15..13=7 12=ignore 11..2=ignore
diff --git a/opcodes-rvc-pseudo b/opcodes-rvc-pseudo
index cdc0127..a357a03 100644
--- a/opcodes-rvc-pseudo
+++ b/opcodes-rvc-pseudo
@@ -1,30 +1,14 @@
# these aren't really pseudo-ops, but they overlay other encodings,
# so they are here to prevent parse-opcodes from barfing
+@c.jr 1..0=0 15..13=0 12=0 11..7=ignore 6..2=0
+@c.jalr 1..0=0 15..13=0 12=1 11..7=ignore 6..2=0
@c.ebreak 1..0=0 15..13=0 12=1 11..7=0 6..2=0
-@c.jr 1..0=2 15..13=4 12=0 11..7=ignore 6..2=0
-@c.jalr 1..0=2 15..13=5 12=0 11..7=ignore 6..2=0
-@c.addi16sp 1..0=2 15..13=6 12=ignore 11..7=0 6..2=ignore
-
-# C0 encoding space, RV32C-only
-@c.xor 1..0=0 15..13=3 12..10=0 9..7=ignore 6..5=0 4..2=ignore
-@c.sra 1..0=0 15..13=3 12..10=0 9..7=ignore 6..5=1 4..2=ignore
-@c.sll 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=0 4..2=ignore
-@c.srl 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=1 4..2=ignore
-@c.slt 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=2 4..2=ignore
-@c.sltu 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=3 4..2=ignore
-@c.sllr 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=0 4..2=ignore
-@c.srlr 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=1 4..2=ignore
-@c.sltr 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=2 4..2=ignore
-@c.sltur 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=3 4..2=ignore
-
-# C1 encoding space, RV32C-only
-@c.bltz 1..0=1 15..13=3 12=ignore 11..2=ignore
-@c.bgez 1..0=1 15..13=7 12=ignore 11..2=ignore
-@c.addin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=0 4..2=ignore
-@c.xorin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=1 4..2=ignore
-@c.orin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=2 4..2=ignore
-@c.andin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=3 4..2=ignore
-
-# C2 encoding space, RV32C-only
-@c.andi 1..0=2 15..13=7 12=ignore 11..2=ignore
+@c.addi16sp 1..0=2 15..13=5 12=ignore 11..7=0 6..2=ignore
+@c.nop 1..0=2 15..13=6 12=0 11..7=0 6..2=0
+
+# RV64C
+@c.sd 1..0=0 15..13=3 12=ignore 11..2=ignore # c.fsw for RV32
+@c.ld 1..0=0 15..13=7 12=ignore 11..2=ignore # c.flw for RV32
+@c.sdsp 1..0=1 15..13=3 12=ignore 11..2=ignore # c.fswsp for RV32
+@c.ldsp 1..0=1 15..13=7 12=ignore 11..2=ignore # c.flwsp for RV32
diff --git a/parse-opcodes b/parse-opcodes
index b6a2430..790b9e4 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -7,6 +7,7 @@ import tokenize
namelist = []
match = {}
mask = {}
+pseudos = {}
arguments = {}
arglut = {}
@@ -819,9 +820,11 @@ for line in sys.stdin:
if not (cover == 0xFFFFFFFF or cover == 0xFFFF):
sys.exit("%s: not all bits are covered" % name)
- if not pseudo:
+ if pseudo:
+ pseudos[name] = 1
+ else:
for name2,match2 in match.iteritems():
- if (match2 & mymask) == mymatch:
+ if name2 not in pseudos and (match2 & mymask) == mymatch:
sys.exit("%s and %s overlap" % (name,name2))
mask[name] = mymask