| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 26 hours | add missing sdt/sie interaction when writing mstatus directly | Ved Shanbhogue | 1 | -3/+2 | |
| 4 days | Fix ignored-attributes warning for unique_ptr declaration | Joseph Faulls | 1 | -1/+1 | |
| The attribute `__nonnull` was added to `fclose` in glibc 2.38, which causes a warning when using its `decltype` on a template argument. | |||||
| 5 days | update encoding.h to get rid of erroneous define | Parshintsev Anatoly | 1 | -2/+2 | |
| 2024-10-04 | Updated load/store pair for RV32 to v0.10 | Christian Herber | 6 | -6/+6 | |
| - renamed Zcmlsd to Zclsd - bumped version number | |||||
| 2024-10-02 | fix typos | Yang Hau | 3 | -4/+4 | |
| 2024-09-27 | Merge pull request #1819 from riscv-software-src/ss-cbo-fault | Andrew Waterman | 2 | -5/+6 | |
| Raise store/AMO access fault on CBO to shadow-stack page | |||||
| 2024-09-27 | refactor: Merge halt and halt_on_reset variables in processor_t | YenHaoChen | 3 | -5/+2 | |
| 2024-09-27 | refactor: Move halt out of dcsr | YenHaoChen | 5 | -5/+4 | |
| Suggested in https://github.com/riscv-software-src/riscv-isa-sim/pull/1816#pullrequestreview-2331806142. | |||||
| 2024-09-26 | Raise store/AMO access fault on CBO to shadow-stack page | Andrew Waterman | 2 | -5/+6 | |
| Proliferating the access_flags isn't ideal, but it wasn't clear how better to handle this case. | |||||
| 2024-09-26 | Only enter debug mode once with -H flag (halt_on_reset) | YenHaoChen | 1 | -0/+1 | |
| 2024-09-18 | Merge pull request #1804 from ved-rivos/ssdbltrp_typo | Andrew Waterman | 1 | -1/+1 | |
| Fix error in reading right sstatus | |||||
| 2024-09-17 | fix error in reading right sstatus | Ved Shanbhogue | 1 | -1/+1 | |
| 2024-09-14 | Remove --with-priv compile flag | Jerry Zhao | 2 | -6/+1 | |
| 2024-09-14 | Remove --with-isa compile-time option | Jerry Zhao | 2 | -6/+1 | |
| 2024-09-11 | Merge pull request #1796 from cyyself/tmp_mcountinhibit | Andrew Waterman | 4 | -4/+19 | |
| add support for mcountinhibit CSR | |||||
| 2024-09-09 | Only implement one solution for native triggers. | Tim Newsome | 2 | -15/+29 | |
| When S-mode is present, use option 1 (disable triggers in M-mode unless MIE is set) from the Debug Spec. When S-mode is not present, use option 2 (implement mte and mpte bits in tcontrol). See discussion in #1777. | |||||
| 2024-09-09 | triggers: Move allow_action() into common_match() | Tim Newsome | 2 | -23/+28 | |
| They are always called together, and now we get the previous privilege behavior in both. | |||||
| 2024-09-05 | Make allow_action() take proc instead of state | Tim Newsome | 2 | -6/+7 | |
| 2024-09-05 | Work if tcontrol doesn't exist. | Tim Newsome | 3 | -3/+10 | |
| 2024-09-06 | add support for mcountinhibit CSR | Yangyu Chen | 4 | -4/+19 | |
| We hardwired mcountinihibit to 0 previously. Now, we implemented it. Signed-off-by: Yangyu Chen <cyy@cyyself.name> | |||||
| 2024-09-02 | Merge pull request #1788 from riscv-software-src/support-larger-addresses | Andrew Waterman | 3 | -4/+7 | |
| Lift restriction on physical-address size | |||||
| 2024-08-30 | Merge pull request #1779 from rtwfroody/trigger_timing | Andrew Waterman | 1 | -1/+8 | |
| For mcontrol6, default to BEFORE timing. | |||||
| 2024-08-29 | pointer masking: Always apply sstatus.MXR regardless of effective V | YenHaoChen | 1 | -1/+1 | |
| ISA spec says "Setting MXR at HS-level overrides both VS-stage and G-stage execute-only permissions." | |||||
| 2024-08-28 | pointer masking: Consider effective v bit instead of current v bit | YenHaoChen | 1 | -1/+1 | |
| A previous commit removes the effectiveness of MPRV to MXR. (https://github.com/riscv-software-src/riscv-isa-sim/pull/1784) However, the removal implies the MPRV affects point masking individually, and the MXR should consider the effective v bit. | |||||
| 2024-08-27 | Merge pull request #1787 from riscv-software-src/fix-cfg-priv | Jerry Zhao | 1 | -1/+1 | |
| 2024-08-27 | Lift restriction on physical-address size | Andrew Waterman | 2 | -2/+3 | |
| It remains true that PTEs can only represent addresses >= 2^56, but there's no need to impose that constraint on untranslated accesses. | |||||
| 2024-08-27 | Check size_t bounds overflow in create_mem_region | Andrew Waterman | 1 | -2/+4 | |
| 2024-08-27 | Merge pull request #1786 from YenHaoChen/pr-mcontrol | Andrew Waterman | 2 | -6/+8 | |
| triggers: Let mcontrol.match be default (0/equal) if maskmax is 0 | |||||
| 2024-08-27 | Use cmdline --priv flag when parsing proc configurations from DTB | Jerry Zhao | 1 | -1/+1 | |
| 2024-08-27 | triggers: Let mcontrol.match be default (0/equal) if maskmax is 0 | YenHaoChen | 2 | -5/+6 | |
| 2024-08-27 | triggers: mcontrol: refactor: Add mcontrol_t::maskmax | YenHaoChen | 2 | -1/+2 | |
| 2024-08-26 | pointer masking: Pointer masking does not apply when MXR=1 regardless of ↵ | YenHaoChen | 1 | -1/+1 | |
| MPRV in v1.0.0-rc2 Reference: https://github.com/riscv/riscv-j-extension/issues/70 | |||||
| 2024-08-23 | Fix exception priority for RV32E JAL/JALR | Andrew Waterman | 3 | -0/+3 | |
| 2024-08-23 | Fix exception priority for RV32E loads and AMOs | Andrew Waterman | 1 | -1/+1 | |
| 2024-08-23 | Refactor insn_template to be more DRY | Andrew Waterman | 1 | -24/+23 | |
| 2024-08-20 | For mcontrol6, default to BEFORE timing. | Tim Newsome | 1 | -1/+8 | |
| The existing implementation would end up using AFTER even for instruction execute and data store triggers, which is not desirable. | |||||
| 2024-08-19 | Merge pull request #1771 from rtwfroody/match_mask | Andrew Waterman | 1 | -4/+8 | |
| Fix mcontrol6 mask low/high operations. | |||||
| 2024-08-19 | Fix mcontrol6 mask low/high operations. | Tim Newsome | 1 | -4/+8 | |
| I doubt this code was ever tested, and this change isn't tested either, because OpenOCD doesn't use this trigger type. This problem was reported in https://github.com/riscv/riscv-debug-spec/issues/1057 | |||||
| 2024-08-18 | Merge pull request #1722 from ved-rivos/smdbltrp | Andrew Waterman | 10 | -20/+92 | |
| Add Smdbltrp | |||||
| 2024-08-18 | pointer masking: refactor: Use xlen to avoid sketchy, hardcoded number 64 | YenHaoChen | 1 | -1/+2 | |
| 2024-08-16 | pointer masking: Fix: Let transformed_addr of fetching be unchanged | YenHaoChen | 1 | -4/+5 | |
| The transformation does not apply to implicit accesses such as instruction fetches. | |||||
| 2024-08-12 | Fix a typo in ↵ | YenHaoChen | 1 | -1/+1 | |
| https://github.com/riscv-software-src/riscv-isa-sim/pull/1721/commits/f11bd7b511d7909f0291589e3aaab720ededdc8a | |||||
| 2024-08-09 | Use ordered map for commit log | Andrew Waterman | 1 | -1/+1 | |
| In general, unordered maps should not be used for iteration, only for lookups. In this case, using an ordered map guarantees that the order in which writes are logged is consistent for a given instruction. Resolves #1499 | |||||
| 2024-08-07 | Add Smdbltrp | Ved Shanbhogue | 10 | -20/+92 | |
| 2024-08-04 | Merge pull request #1758 from riscv-software-src/csr-init-fixes | Andrew Waterman | 5 | -407/+398 | |
| Only supply CSRs if corresponding extensions are enabled | |||||
| 2024-08-05 | Let MXR not affect implicit memory access for VS-stage address translation | YenHaoChen | 1 | -1/+1 | |
| The behavior of MXR is clarified in https://github.com/riscv/riscv-isa-manual/pull/1543. | |||||
| 2024-08-01 | Only add CSRs if corresponding extensions are enabled | Andrew Waterman | 1 | -55/+57 | |
| 2024-08-01 | Remove boilerplate from most CSR instantiations | Andrew Waterman | 2 | -62/+34 | |
| 2024-08-01 | Refactor initialization of mode-specific CSRs | Andrew Waterman | 1 | -20/+18 | |
| The if-statements are boilerplate. | |||||
| 2024-08-01 | Add CSRs through an interface, rather than mutating csrmap | Andrew Waterman | 3 | -148/+156 | |
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index : riscv-tools/riscv-isa-sim.git | |
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