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20 hoursMerge pull request #2227 from riscv-software-src/fix-2221HEADmasterAndrew Waterman1-4/+4
21 hoursRaise correct trap in U-mode on indirect CSRs when !mstateen.csrindAndrew Waterman1-4/+4
9 daysMerge pull request #2221 from DymShanks/fix/vu-mode-siregAndrew Waterman1-0/+4
10 daysFix: Enforce virtual_instruction trap for VU-mode indirect CSR accessDymShanks1-0/+4
11 daysMerge pull request #2223 from riscv-software-src/fix-depsAndrew Waterman5-423/+384
11 daysHave Zabha imply extensions rather than erroring if not presentAndrew Waterman1-12/+3
11 daysHave ZC* imply extensions rather than erroring if not presentAndrew Waterman1-5/+5
11 daysHave Zvfofp4min imply extensions rather than erroring if not presentAndrew Waterman1-8/+2
11 daysClean up handling of ZcfAndrew Waterman2-12/+10
11 daysHave V imply extensions rather than erroring if not presentAndrew Waterman1-10/+6
11 daysHave Z[v]fbfmin imply extensions rather than erroring if not presentAndrew Waterman1-16/+6
11 daysHave Zvfhmin imply extensions rather than erroring if not presentAndrew Waterman1-9/+2
11 daysFactor out add_extension methodAndrew Waterman2-343/+351
11 daysHave Zfhmin imply extensions rather than erroring if not presentAndrew Waterman1-12/+11
11 daysHave Zclsd imply extensions rather than erroring if not presentAndrew Waterman1-9/+8
11 daysHave Zicfiss imply extensions rather than erroring if not presentAndrew Waterman1-10/+4
11 daysZicfiss depends on ZaamoAndrew Waterman3-2/+1
11 daysDon't log commits in snippy testsAndrew Waterman1-1/+1
11 daysMerge pull request #2224 from riscv-software-src/add-vector-testAndrew Waterman2-0/+30
11 daysEcho CI commands to ease debuggingAndrew Waterman1-0/+1
11 daysAdd simple vector extension test to CIAndrew Waterman2-0/+29
2026-01-21Merge pull request #2198 from riscv-software-src/fix-amocas-qAndrew Waterman1-34/+12
2026-01-21Make reg_from_bytes a bit less grossAndrew Waterman1-22/+6
2026-01-21DRY in logging codeAndrew Waterman1-9/+4
2026-01-21Fix triggers for accesses wider than XLENAndrew Waterman1-3/+2
2026-01-20Merge pull request #2216 from pointerliu/fix-tw-readAndrew Waterman1-1/+2
2026-01-21csrs.cc: if no U-mode, mstatus.tw is read-only 0pointerliu1-1/+2
2026-01-13Merge pull request #2208 from riscv-software-src/remove-greviAndrew Waterman13-360/+412
2026-01-13Don't rely on definition of unratified bitmanip opcodesAndrew Waterman13-333/+389
2026-01-13Clean up grevi/gorci/shfli/unshfli implementationsAndrew Waterman4-29/+25
2026-01-12Merge pull request #2205 from Steven-Li-Xiaogang/masterAndrew Waterman1-6/+8
2026-01-03correct smcdeleg indirect CSRs address accessed via sireg*steven1-6/+8
2026-01-02Merge pull request #2191 from Steven-Li-Xiaogang/masterAndrew Waterman2-4/+6
2026-01-02Merge pull request #2204 from mmhus/mmhus/mireg-sireg-fixesAndrew Waterman3-54/+82
2026-01-02fixed smcdeleg to be limited to, holds a value in the range 0x40-0x5F, from p...muhammad.moiz.hussain1-35/+38
2026-01-02changed minstret to instret and mcycle to cyclemuhammad.moiz.hussain2-18/+34
2026-01-02when AIA throw virt intruction exception and V=1 & vs-mode, otherwise throw i...muhammad.moiz.hussain1-1/+10
2025-12-31Merge pull request #2193 from mslijepc/mslijepc_20251224_zicclsmAndrew Waterman6-5/+4
2025-12-29removed cfg.misaligned optionmslijepc4-5/+1
2025-12-27Merge pull request #2197 from omerguzelelectronicguy/masterAndrew Waterman2-3/+5
2025-12-27Merge pull request #2161 from fkhaidari/fk/trig-algo-modAndrew Waterman4-75/+116
2025-12-26unnecessary dtb to dts operation removedÖmer Güzel2-3/+5
2025-12-25Update trigger behavior for memory accesses to match recommended debug specif...Farid Khaydari4-75/+116
2025-12-24Merge pull request #2194 from riscv-software-src/fix-2192Andrew Waterman1-1/+0
2025-12-24Remove declaration for undefined functionAndrew Waterman1-1/+0
2025-12-24added support for zicclsmmslijepc3-1/+4
2025-12-24register indirection CSRs 'iprio0~iprio15' when Smaia/Ssaia supportedsteven2-4/+6
2025-12-23Merge pull request #2189 from Steven-Li-Xiaogang/masterAndrew Waterman1-5/+1
2025-12-23Better to raise an illegal-instruction exception upon accessing sireg*steven1-5/+1
2025-12-17Merge pull request #2187 from riscv-software-src/2186-reduxAndrew Waterman1-4/+4