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:
riscv-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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6 hours
Merge pull request #1839 from ved-rivos/issue_1838
HEAD
master
Andrew Waterman
1
-3
/
+2
14 hours
add missing sdt/sie interaction when writing mstatus directly
Ved Shanbhogue
1
-3
/
+2
3 days
Merge pull request #1835 from joe-rivos/fix-ignored-attributes-warning
Andrew Waterman
1
-1
/
+1
4 days
Fix ignored-attributes warning for unique_ptr declaration
Joseph Faulls
1
-1
/
+1
4 days
Merge pull request #1834 from aap-sc/master
Andrew Waterman
1
-2
/
+2
4 days
update encoding.h to get rid of erroneous define
Parshintsev Anatoly
1
-2
/
+2
2024-10-04
Merge pull request #1829 from NXP/update-zilsd-to-v0.10
Andrew Waterman
9
-15
/
+15
2024-10-04
Updated load/store pair for RV32 to v0.10
Christian Herber
9
-15
/
+15
2024-10-02
Merge pull request #1822 from howjmay/typos
Andrew Waterman
5
-6
/
+6
2024-10-02
fix typos
Yang Hau
5
-6
/
+6
2024-10-01
Merge pull request #1823 from YenHaoChen/pr-halt
Andrew Waterman
1
-3
/
+2
2024-10-01
Merge pull request #1826 from riscv-software-src/fix-1825
Andrew Waterman
1
-7
/
+39
2024-10-01
Change -H flag into --halted
YenHaoChen
1
-3
/
+2
2024-09-30
Fix f64_to_bf16 raising underflow when it shouldn't
Andrew Waterman
1
-7
/
+39
2024-09-27
Merge pull request #1819 from riscv-software-src/ss-cbo-fault
Andrew Waterman
2
-5
/
+6
2024-09-26
Merge pull request #1820 from YenHaoChen/pr-halt
Andrew Waterman
4
-6
/
+2
2024-09-27
refactor: Merge halt and halt_on_reset variables in processor_t
YenHaoChen
3
-5
/
+2
2024-09-27
refactor: Move halt out of dcsr
YenHaoChen
5
-5
/
+4
2024-09-26
Raise store/AMO access fault on CBO to shadow-stack page
Andrew Waterman
2
-5
/
+6
2024-09-26
Merge pull request #1816 from YenHaoChen/pr-halt
Andrew Waterman
1
-0
/
+1
2024-09-26
Only enter debug mode once with -H flag (halt_on_reset)
YenHaoChen
1
-0
/
+1
2024-09-20
Merge pull request #1812 from riscv-software-src/fix-1810
Andrew Waterman
1
-2
/
+22
2024-09-20
Validate Zvl ISA string correctly
Andrew Waterman
1
-2
/
+22
2024-09-20
Merge pull request #1811 from riscv-software-src/fix-1810
Andrew Waterman
1
-1
/
+1
2024-09-20
Validate Zvl ISA string correctly
Andrew Waterman
1
-1
/
+1
2024-09-18
Merge pull request #1804 from ved-rivos/ssdbltrp_typo
Andrew Waterman
1
-1
/
+1
2024-09-17
fix error in reading right sstatus
Ved Shanbhogue
1
-1
/
+1
2024-09-14
Merge pull request #1807 from riscv-software-src/remove-compile-flags
Jerry Zhao
7
-53
/
+5
2024-09-14
Remove leftover config.h includes in dasm/log-parser
Jerry Zhao
2
-2
/
+0
2024-09-14
Remove --with-priv compile flag
Jerry Zhao
5
-25
/
+2
2024-09-14
Remove --with-isa compile-time option
Jerry Zhao
6
-26
/
+3
2024-09-11
Merge pull request #1796 from cyyself/tmp_mcountinhibit
Andrew Waterman
4
-4
/
+19
2024-09-11
Merge pull request #1793 from rtwfroody/native_triggers2
YenHaoChen
5
-26
/
+53
2024-09-09
Only implement one solution for native triggers.
Tim Newsome
2
-15
/
+29
2024-09-09
triggers: Move allow_action() into common_match()
Tim Newsome
2
-23
/
+28
2024-09-05
Make allow_action() take proc instead of state
Tim Newsome
2
-6
/
+7
2024-09-05
Work if tcontrol doesn't exist.
Tim Newsome
3
-3
/
+10
2024-09-06
add support for mcountinhibit CSR
Yangyu Chen
4
-4
/
+19
2024-09-02
Merge pull request #1797 from YenHaoChen/pr-vector
Andrew Waterman
1
-20
/
+48
2024-09-03
vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector wideni...
YenHaoChen
1
-4
/
+4
2024-09-03
vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single...
YenHaoChen
1
-8
/
+18
2024-09-03
vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector wideni...
YenHaoChen
1
-4
/
+6
2024-09-03
vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single...
YenHaoChen
1
-4
/
+20
2024-09-02
Merge pull request #1788 from riscv-software-src/support-larger-addresses
Andrew Waterman
4
-43
/
+36
2024-08-30
Merge pull request #1779 from rtwfroody/trigger_timing
Andrew Waterman
1
-1
/
+8
2024-08-29
Merge pull request #1791 from YenHaoChen/pr-pm
Andrew Waterman
1
-1
/
+1
2024-08-29
pointer masking: Always apply sstatus.MXR regardless of effective V
YenHaoChen
1
-1
/
+1
2024-08-28
Merge pull request #1789 from YenHaoChen/pr-pm
Andrew Waterman
1
-1
/
+1
2024-08-28
pointer masking: Consider effective v bit instead of current v bit
YenHaoChen
1
-1
/
+1
2024-08-27
Merge pull request #1787 from riscv-software-src/fix-cfg-priv
Jerry Zhao
1
-1
/
+1
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