riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2015-09-20	Remove Hwacha v3 tests	Andrew Waterman	13	-1127/+0

2015-03-25	split out S-mode tests and M-mode tests	Yunsup Lee	12	-40/+18

2015-03-17	relay hwacha cause/aux to scause/sbadaddr	Yunsup Lee	10	-20/+20

2015-03-16	revamp vector tests with new privileged spec, and add scalar pt tests	Yunsup Lee	12	-133/+29

2015-01-09	Add LICENSE	Andrew Waterman	12	-0/+24

2014-04-08	Adjust hwacha misaligned instruction test to ignore lower 2 bits in ↵	Stephen Twigg	1	-0/+2
	comparisons to account for impl differences.
2014-01-31	Reference TESTNUM instead of x28 directly	Andrew Waterman	10	-50/+50

2013-11-24	Update to new privileged ISA	Andrew Waterman	12	-59/+61

2013-11-05	correctly set SR_EA bit for all vector physical supervisor tests	Yunsup Lee	12	-0/+14

2013-10-17	add hwacha exception support	Yunsup Lee	13	-89/+406

2013-10-10	revamp hwacha tests	Yunsup Lee	7	-27/+41

2013-04-24	cleanup Makefiles in isa	Yunsup Lee	2	-101/+11

2013-04-22	initial commit	Yunsup Lee	10	-0/+970