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2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵SLAMET RIANTO2-0/+2
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵SLAMET RIANTO2-0/+14
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman1-2/+0
Resolves #303
2020-03-21Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5Andrew Waterman1-7/+7
2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-11Add comment explaining convoluted rv64mi-p-scall behaviorAndrew Waterman1-0/+6
2020-03-11Revert "scall: make the intention of the test in machine mode more clear (#246)"Andrew Waterman1-6/+1
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256
2020-03-11Setup a multilevel page table to avoid misaligned superpages caused by ↵Cedric Orban1-0/+4
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned
2020-03-06Don't assume reset state of mscratch (#254)Paul Donahue1-1/+1
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset
2020-02-21scall: make the intention of the test in machine mode more clear (#246)Nils Asmussen1-1/+6
2020-02-20Fix rv64mi-p-csr on systems with FPUsAndrew Waterman1-2/+3
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because of the value of TESTNUM at the point an expected exception was taken. Fix by moving the new tests earlier in the program.
2020-01-31Added CSR test cases on whether writing 0 to CSR works, as that might get ↵Torbjørn Viem Ness1-0/+2
overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236)
2019-11-04Remove cruft from icache-alias testAndrew Waterman1-35/+0
2019-11-04Add rv64si-p-icache-aliasAndrew Waterman2-0/+177
This test checks that an I$ appears to be physically indexed.
2018-08-21Changing the register mstatus is read into (#152)Srivatsa Yogendra1-2/+2
The mstatus reading overwrites the expected user mode cause value.
2018-08-20Revert "Fix to solve the failing tests shamt, csr and scall (#151)"Andrew Waterman2-52/+5
This reverts commit 31a91823b7c7becacd06c9c32e44180eea5e4fe7. These changes should be made to the test environment, not the tests themselves.
2018-08-17Fix to solve the failing tests shamt, csr and scall (#151)Srivatsa Yogendra2-5/+52
* making mtvec_handler global * Adding the pmp configuration inst The PMP config instructions are added as the test jumps to user mode * Adding pmp config inst Adding pmp config instructions as the test jumps to user mode * changing to PMP macros * changing to PMP Macros * moving the #endif after pmp initialization * Removing the unwanted label
2018-03-21Make misa.C test conform to Hauser proposalAndrew Waterman1-43/+10
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7
2018-02-27Add test for clearing misa.C while PC is misaligned (#117)Andrew Waterman1-1/+79
See https://github.com/riscv/riscv-isa-manual/pull/139
2017-11-27Rename sbadaddr to satpAndrew Waterman1-1/+1
2017-11-22Check sepc for rv64si/scall test. (#107)Christopher Celio1-0/+4
Closes #105.
2017-11-11Make sure that code is 4-byte aligned before disabling rvc (#100)Andrew Waterman1-0/+1
2017-11-09Make rv64mi-p-ecall work when U-mode is not presentAndrew Waterman1-1/+17
2017-11-09Use mstatus.MPP to check existence of U-modeAndrew Waterman1-5/+6
misa is allowed to be hardwired to 0, so checking its U bit could incorrectly suggest that U-mode is not supported.
2017-11-01SBREAK test now checks EPC value. (#92)Christopher Celio1-0/+4
Closes #89
2017-10-30Declare trap handlers as global symbols. (#87)Richard Xia5-0/+5
This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit.
2017-10-26Verify that mtval/stval is written correctly on misaligned fetchAndrew Waterman1-1/+9
2017-10-26Fix rv64mi-csr for the case where U-mode is not available. (#86)Richard Xia1-0/+16
2017-09-01Improve ma_fetch test to cover JAL and branchesAndrew Waterman1-1/+48
2017-08-07rv64[ms]i-csr: Only emit F instructions when compiled for F.Richard Xia1-1/+6
2017-05-05Check UXL in sstatusAndrew Waterman1-0/+5
2017-05-05Test that superpage PTEs trap when PPN LSBs are setAndrew Waterman1-0/+18
2017-05-05Regularize control flow in dirty-bit testAndrew Waterman1-8/+12
2017-03-30Expand dirty-bit test to test MPRV and SUMAndrew Waterman1-27/+30
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-1/+1
2017-03-21Allow supervisor access to user pages in dirty-bit testAndrew Waterman1-1/+1
2017-03-09Permit flexible dirty-bit behaviorAndrew Waterman1-16/+26
2016-11-01Make sure FP stores don't write memory if mstatus.FS=0.Andrew Waterman1-8/+22
2016-08-26Update to new breakpoint & counter specAndrew Waterman1-6/+6
2016-07-22skip user-mode trap tests in rv32mi/rv64mi-p-csr if no user modeHoward Mao1-0/+9
2016-07-22Move dirty bit test to rv64si directoryAndrew Waterman2-0/+94
Not sure this is quite right, since the test technically runs in M-mode. Also, remove unused rdnpc/example tests.
2016-07-22Make ma_fetch test robust against code size changesAndrew Waterman1-2/+4
2016-07-11Remove instruction width assumptions to support RVCAndrew Waterman4-6/+6
2016-07-07Update WFI test for priv v1.9Andrew Waterman1-2/+3
2016-05-02Remove incorrect M-mode WFI testAndrew Waterman1-9/+0
MSIP isn't supposed to be writable locally!
2016-04-30ERET -> xRET; new memory mapAndrew Waterman4-17/+13
For now, we no longer build hex files, because the programs don't start at address 0. This decision will likely be revisited.
2016-03-03Make WFI test more strictAndrew Waterman1-3/+1
2016-03-03Some S-mode tests really only belong in M-modeAndrew Waterman4-154/+9
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