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| author | Andrew Waterman <aswaterman@gmail.com> | 2017-11-11 16:15:22 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-11 16:15:22 -0800 |
| commit | 6cd865488a4ef49f0f68f46ef619f097a0ae9ec0 (patch) | |
| tree | 6a2b35c60ef918172c316f0de45d98df0cb2d648 /isa/rv64si | |
| parent | d9b4071ea4a9a2fe84a51443250184f51e931ac2 (diff) | |
| download | riscv-tests-6cd865488a4ef49f0f68f46ef619f097a0ae9ec0.zip riscv-tests-6cd865488a4ef49f0f68f46ef619f097a0ae9ec0.tar.gz riscv-tests-6cd865488a4ef49f0f68f46ef619f097a0ae9ec0.tar.bz2 | |
Make sure that code is 4-byte aligned before disabling rvc (#100)
Diffstat (limited to 'isa/rv64si')
| -rw-r--r-- | isa/rv64si/ma_fetch.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index 5943456..cd5a22d 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -23,6 +23,7 @@ RVTEST_CODE_BEGIN #define stvec_handler mtvec_handler #endif + .align 2 .option norvc # Without RVC, the jalr should trap, and the handler will skip ahead. |