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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-11 17:45:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-07-11 17:45:16 -0700 |
| commit | 089f4aae4836af1f3f530fbedc3a43a685eae0d1 (patch) | |
| tree | 76bc328ba3e17aa6caab7957afb250c6ab0eb6c6 /isa/rv64si | |
| parent | a5b7f805c111e14a1478153147a57283a0b9e45d (diff) | |
| download | riscv-tests-089f4aae4836af1f3f530fbedc3a43a685eae0d1.zip riscv-tests-089f4aae4836af1f3f530fbedc3a43a685eae0d1.tar.gz riscv-tests-089f4aae4836af1f3f530fbedc3a43a685eae0d1.tar.bz2 | |
Remove instruction width assumptions to support RVC
Diffstat (limited to 'isa/rv64si')
| -rw-r--r-- | isa/rv64si/csr.S | 1 | ||||
| -rw-r--r-- | isa/rv64si/ma_fetch.S | 1 | ||||
| -rw-r--r-- | isa/rv64si/sbreak.S | 9 | ||||
| -rw-r--r-- | isa/rv64si/scall.S | 1 |
4 files changed, 6 insertions, 6 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 35fc99a..3858daa 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -61,6 +61,7 @@ RVTEST_CODE_BEGIN # We should only fall through to this if scall failed. TEST_PASSFAIL + .align 2 stvec_handler: # Trapping on tests 10 and 11 is good news. # Note that since the test didn't complete, TESTNUM is smaller by 1. diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index a97eecb..544daa0 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -63,6 +63,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL + .align 2 stvec_handler: # tests 2 and 4 should trap li a0, 2 diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S index 99240be..c2a6e49 100644 --- a/isa/rv64si/sbreak.S +++ b/isa/rv64si/sbreak.S @@ -23,21 +23,18 @@ RVTEST_CODE_BEGIN #endif li TESTNUM, 2 + sbreak j fail - j pass - TEST_PASSFAIL + .align 2 stvec_handler: li t1, CAUSE_BREAKPOINT csrr t0, scause bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret + j pass RVTEST_CODE_END diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S index f4752d1..82ba7c0 100644 --- a/isa/rv64si/scall.S +++ b/isa/rv64si/scall.S @@ -39,6 +39,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL + .align 2 stvec_handler: li t1, CAUSE_USER_ECALL csrr t0, scause |