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Adds four RV64 hypervisor tests exercising implicit G-stage faults raised
during VS-stage page table walks:
- 2-stage_translation_implicit_load_error
- 2-stage_translation_implicit_load_error_hs
- 2-stage_translation_implicit_store_error
- 2-stage_translation_implicit_store_error_hs
The load variants trigger the fault by leaving the G-stage PTE invalid
(no PTE_V), causing the implicit PTE read during the VS-stage walk to
fault. The store variants omit PTE_W on the G-stage PTE, so G-stage
grants read but denies write, causing the implicit PTE store for the
A/D writeback to fail. These require hardware A/D updates, which occur
when Svadu is enabled via ADUE.
Each test checks mcause/scause, mtval/stval, and mtval2/htval and
verifies that mtinst/htinst contains the expected pseudoinstruction:
- 0x3000 — 64-bit implicit VS-stage PTE load
- 0x3020 — 64-bit implicit VS-stage PTE store
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