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Author
Files
Lines
2020-01-15
Force DMI busy in all tests. (#235)
Tim Newsome
2
-15
/
+44
2020-01-09
Smoke test virtual address translation support. (#233)
Tim Newsome
6
-13
/
+231
2019-12-18
Hardcode misa values for all spike targets. (#227)
Tim Newsome
9
-7
/
+27
2019-12-18
Tell people where to get software. (#226)
Tim Newsome
1
-3
/
+9
2019-12-10
Improve parallellism in debug test Makefile (#223)
Tim Newsome
2
-15
/
+28
2019-12-02
Use a small binary to set up HiFive Unleashed. (#221)
Tim Newsome
3
-10
/
+10
2019-11-22
Move to Python 3. (#218)
Tim Newsome
4
-75
/
+78
2019-10-15
Add support to run all tests against HiFive Unleashed. (#212)
Tim Newsome
7
-3
/
+191
2019-10-09
Remove ocd_ prefix. (#210)
Tim Newsome
4
-4
/
+4
2019-09-24
Redo the debug README. (#205)
Tim Newsome
1
-26
/
+19
2019-09-24
Look for binaries in $PATH. (#208)
Tim Newsome
1
-7
/
+4
2019-08-02
Miscellaneous minor test improvements (#199)
Tim Newsome
4
-19
/
+20
2019-07-15
Make tests work with RV32E targets. (#196)
Tim Newsome
5
-27
/
+45
2019-07-15
Use work area in spike-1 to cover CRC algorithm. (#195)
Tim Newsome
2
-1
/
+6
2019-06-14
Work better with mainline gdb (#192)
Tim Newsome
2
-23
/
+46
2019-05-16
Cover with/without halt groups. (#191)
Tim Newsome
5
-12
/
+20
2019-04-08
Test lack of abstract CSR access. (#187)
Tim Newsome
7
-8
/
+14
2019-04-04
Test simultaneous resume using hasel. (#186)
Tim Newsome
9
-31
/
+51
2019-03-11
Add SmpSimultaneousRunHalt test. (#181)
Tim Newsome
4
-10
/
+89
2019-02-14
Test `-rtos hwthread` (#178)
Tim Newsome
6
-22
/
+81
2019-01-25
Merge pull request #175 from riscv/test_rti
Carsten Gosvig
7
-7
/
+17
2019-01-07
Fail on unsupported SREC type.
Tim Newsome
1
-0
/
+2
2018-12-31
Add testing of run-test/idle cases.
Tim Newsome
7
-7
/
+17
2018-12-31
Fix MemTestBlock
Tim Newsome
1
-20
/
+41
2018-12-03
Reduce download size a bit.
Tim Newsome
2
-6
/
+9
2018-11-30
Use more than 1KB for download test.
Tim Newsome
1
-1
/
+1
2018-11-16
Make pylint happy.
Tim Newsome
1
-3
/
+6
2018-11-14
Merge pull request #165 from riscv/flash
Tim Newsome
7
-18
/
+103
2018-11-14
Cleanup and renamed test flag to invalid_memory_returns_zero
cgsfv
4
-6
/
+6
2018-11-13
Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix
cgsfv
4
-2
/
+59
2018-11-12
Simpler/more idiomatic way to keep string on stack
Tim Newsome
1
-4
/
+1
2018-10-31
Add HiFive1-flash target configuration.
Tim Newsome
2
-0
/
+59
2018-10-31
Fix remaining tests to work from flash:
Tim Newsome
2
-6
/
+17
2018-10-29
Almost all tests pass with HiFive1-flash
Tim Newsome
2
-4
/
+13
2018-10-29
Tweak debug tests to run out of flash.
Tim Newsome
4
-8
/
+17
2018-10-24
Merge branch 'TriggerLoadAddressInstant'
Tim Newsome
1
-12
/
+1
2018-10-24
Re-enable TriggerStoreAddressInstant
Tim Newsome
1
-12
/
+1
2018-10-05
Make HwWatchpoint test fail on incorrect result.
hw_watchpoint
Tim Newsome
3
-7
/
+10
2018-10-03
Added tests for hw and sw watchpoints
cgsfv
3
-0
/
+88
2018-09-13
Assert if HiFive1 program is too large.
Tim Newsome
1
-0
/
+2
2018-09-13
Put debug test stack in data instead of text
Tim Newsome
1
-0
/
+1
2018-09-03
Merge pull request #156 from riscv/PrivChange
Tim Newsome
1
-27
/
+26
2018-08-31
Fix CustomRegisterTest.
Tim Newsome
2
-5
/
+6
2018-08-29
Add test case for `riscv expose_custom`.
Tim Newsome
12
-0
/
+55
2018-08-28
Reset address translation/perms before PrivChange
Tim Newsome
1
-27
/
+26
2018-08-27
Neuter TriggerStoreAddressInstant
Tim Newsome
1
-1
/
+13
2018-08-27
Make pylint happy.
Tim Newsome
1
-1
/
+2
2018-08-25
Temporarily disabling PrivChange test
Andrew Waterman
1
-22
/
+23
2018-08-23
Make pylint happy with change d1d2d953b5016b465.
Tim Newsome
2
-3
/
+4
2018-08-23
Get all of the log into the final log file
Tim Newsome
1
-6
/
+20
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