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author | Tim Newsome <tim@sifive.com> | 2018-11-14 13:11:46 -0800 |
---|---|---|
committer | GitHub <noreply@github.com> | 2018-11-14 13:11:46 -0800 |
commit | 8a2b5bb543bcfa5e92c2cac1e2cfa7ee6602d7ce (patch) | |
tree | c5c8fce046d2a657df50710f05b77443fbb8cc57 /debug | |
parent | 4dc6acb33b4b8ebf1caa3e19c006ebc41f548d85 (diff) | |
parent | cfab417615b101e1834fe56bcfe9b11b91a6eaea (diff) | |
download | riscv-tests-8a2b5bb543bcfa5e92c2cac1e2cfa7ee6602d7ce.zip riscv-tests-8a2b5bb543bcfa5e92c2cac1e2cfa7ee6602d7ce.tar.gz riscv-tests-8a2b5bb543bcfa5e92c2cac1e2cfa7ee6602d7ce.tar.bz2 |
Merge pull request #165 from riscv/flash
Tweak debug tests to run out of flash.
Diffstat (limited to 'debug')
-rwxr-xr-x | debug/gdbserver.py | 46 | ||||
-rw-r--r-- | debug/programs/debug.c | 2 | ||||
-rw-r--r-- | debug/programs/regs.S | 1 | ||||
-rw-r--r-- | debug/programs/trigger.S | 2 | ||||
-rw-r--r-- | debug/targets/SiFive/HiFive1-flash.lds | 44 | ||||
-rw-r--r-- | debug/targets/SiFive/HiFive1-flash.py | 15 | ||||
-rw-r--r-- | debug/testlib.py | 11 |
7 files changed, 103 insertions, 18 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 0dc87a0..df7bb1c 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -363,9 +363,10 @@ class ProgramTest(GdbSingleHartTest): def setup(self): self.gdb.load() - self.gdb.b("_exit") def exit(self, expected_result=10): + self.gdb.command("delete") + self.gdb.b("_exit") output = self.gdb.c() assertIn("Breakpoint", output) assertIn("_exit", output) @@ -373,10 +374,11 @@ class ProgramTest(GdbSingleHartTest): class ProgramHwWatchpoint(ProgramTest): def test(self): - self.gdb.b("main") + mainbp = self.gdb.b("main") output = self.gdb.c() assertIn("Breakpoint", output) assertIn("main", output) + self.gdb.command("delete %d" % mainbp) self.gdb.watch("counter == 5") # Watchpoint hits when counter becomes 5. output = self.gdb.c() @@ -485,12 +487,14 @@ class DebugExit(DebugTest): class DebugSymbols(DebugTest): def test(self): - self.gdb.b("main") - self.gdb.b("rot13") + bp = self.gdb.b("main") output = self.gdb.c() assertIn(", main ", output) + self.gdb.command("delete %d" % bp) + bp = self.gdb.b("rot13") output = self.gdb.c() assertIn(", rot13 ", output) + self.gdb.command("delete %d" % bp) class DebugBreakpoint(DebugTest): def test(self): @@ -514,6 +518,7 @@ class Hwbp1(DebugTest): self.gdb.b("main") self.gdb.c() + self.gdb.command("delete") self.gdb.hbreak("rot13") # The breakpoint should be hit exactly 2 times. for _ in range(2): @@ -521,6 +526,7 @@ class Hwbp1(DebugTest): self.gdb.p("$pc") assertRegexpMatches(output, r"[bB]reakpoint") assertIn("rot13 ", output) + self.gdb.b("_exit") self.exit() class Hwbp2(DebugTest): @@ -528,6 +534,7 @@ class Hwbp2(DebugTest): if self.hart.instruction_hardware_breakpoint_count < 2: return 'not_applicable' + self.gdb.command("delete") self.gdb.hbreak("main") self.gdb.hbreak("rot13") # We should hit 3 breakpoints. @@ -536,6 +543,8 @@ class Hwbp2(DebugTest): self.gdb.p("$pc") assertRegexpMatches(output, r"[bB]reakpoint") assertIn("%s " % expected, output) + self.gdb.command("delete") + self.gdb.b("_exit") self.exit() class TooManyHwbp(DebugTest): @@ -543,7 +552,7 @@ class TooManyHwbp(DebugTest): for i in range(30): self.gdb.hbreak("*rot13 + %d" % (i * 4)) - output = self.gdb.c() + output = self.gdb.c(checkOutput=False) assertIn("Cannot insert hardware breakpoint", output) # Clean up, otherwise the hardware breakpoints stay set and future # tests may fail. @@ -851,11 +860,13 @@ class TriggerTest(GdbSingleHartTest): compile_args = ("programs/trigger.S", ) def setup(self): self.gdb.load() - self.gdb.b("_exit") self.gdb.b("main") self.gdb.c() + self.gdb.command("delete") def exit(self): + self.gdb.command("delete") + self.gdb.b("_exit") output = self.gdb.c() assertIn("Breakpoint", output) assertIn("_exit", output) @@ -959,23 +970,32 @@ class TriggerDmode(TriggerTest): return triggers def test(self): + # If we want this test to run from flash, we can't have any software + # breakpoints set. + self.gdb.command("hbreak write_load_trigger") - self.gdb.b("clear_triggers") self.gdb.p("$pc=write_store_trigger") output = self.gdb.c() assertIn("write_load_trigger", output) self.check_triggers((1<<6) | (1<<1), 0xdeadbee0) + self.gdb.command("delete") + self.gdb.command("hbreak clear_triggers") output = self.gdb.c() assertIn("clear_triggers", output) self.check_triggers((1<<6) | (1<<0), 0xfeedac00) + self.gdb.command("delete") + self.exit() class RegsTest(GdbSingleHartTest): compile_args = ("programs/regs.S", ) def setup(self): self.gdb.load() - self.gdb.b("main") + main_bp = self.gdb.b("main") + output = self.gdb.c() + assertIn("Breakpoint ", output) + assertIn("main", output) + self.gdb.command("delete %d" % main_bp) self.gdb.b("handle_trap") - self.gdb.c() class WriteGprs(RegsTest): def test(self): @@ -984,16 +1004,16 @@ class WriteGprs(RegsTest): self.gdb.p("$pc=write_regs") for i, r in enumerate(regs): self.gdb.p("$%s=%d" % (r, (0xdeadbeef<<i)+17)) - self.gdb.p("$x1=data") + self.gdb.p("$x1=&data") self.gdb.command("b all_done") output = self.gdb.c() assertIn("Breakpoint ", output) # Just to get this data in the log. - self.gdb.command("x/30gx data") + self.gdb.command("x/30gx &data") self.gdb.command("info registers") for n in range(len(regs)): - assertEqual(self.gdb.x("data+%d" % (8*n), 'g'), + assertEqual(self.gdb.x("(char*)(&data)+%d" % (8*n), 'g'), ((0xdeadbeef<<n)+17) & ((1<<self.hart.xlen)-1)) class WriteCsrs(RegsTest): @@ -1007,7 +1027,7 @@ class WriteCsrs(RegsTest): assertEqual(self.gdb.p("$mscratch"), 123) self.gdb.p("$pc=write_regs") - self.gdb.p("$x1=data") + self.gdb.p("$x1=&data") self.gdb.command("b all_done") self.gdb.command("c") diff --git a/debug/programs/debug.c b/debug/programs/debug.c index 3ba51bc..8a4aa73 100644 --- a/debug/programs/debug.c +++ b/debug/programs/debug.c @@ -53,7 +53,7 @@ int main() volatile int i = 0; int j = 0; - char *fox = "The quick brown fox jumps of the lazy dog."; + char fox[] = "The quick brown fox jumps of the lazy dog."; unsigned int checksum = 0; start: diff --git a/debug/programs/regs.S b/debug/programs/regs.S index 50dafa2..63889dc 100644 --- a/debug/programs/regs.S +++ b/debug/programs/regs.S @@ -52,6 +52,7 @@ write_regs: all_done: j all_done + .section .bss .balign 16 data: .fill 64, 8, 0 diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S index 13f0449..2ccfd21 100644 --- a/debug/programs/trigger.S +++ b/debug/programs/trigger.S @@ -93,7 +93,7 @@ read_triggers: 1: SREG zero, 0(a0) ret - .data + .section .data .align 3 data: .word 0x40 .word 0x41 diff --git a/debug/targets/SiFive/HiFive1-flash.lds b/debug/targets/SiFive/HiFive1-flash.lds new file mode 100644 index 0000000..e4074be --- /dev/null +++ b/debug/targets/SiFive/HiFive1-flash.lds @@ -0,0 +1,44 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY +{ + flash (rxl) : ORIGIN = 0x20400000, LENGTH = 128K + ram (wx) : ORIGIN = 0x80000000, LENGTH = 16K +} + +SECTIONS +{ + flash_text : { + *(.text.entry) + *(.text) + } >flash + + /* data segment */ + .data : { *(.data) } >ram + + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >ram + + /* bss segment */ + __bss_start = .; + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >ram + .bss : { *(.bss) } >ram + __bss_end = .; + + __malloc_start = .; + . = . + 512; + + /* End of uninitalized data segement */ + _end = .; +} + +ENTRY(_start) + +ASSERT(_end < 0x80004000, "program is too large") diff --git a/debug/targets/SiFive/HiFive1-flash.py b/debug/targets/SiFive/HiFive1-flash.py new file mode 100644 index 0000000..06dfcfc --- /dev/null +++ b/debug/targets/SiFive/HiFive1-flash.py @@ -0,0 +1,15 @@ +import targets + +# Like HiFive1, but put code in flash + +class HiFive1FlashHart(targets.Hart): + xlen = 32 + ram = 0x80000000 + ram_size = 16 * 1024 + instruction_hardware_breakpoint_count = 2 + misa = 0x40001105 + link_script_path = "HiFive1-flash.lds" + +class HiFive1Flash(targets.Target): + harts = [HiFive1FlashHart()] + openocd_config_path = "HiFive1.cfg" diff --git a/debug/testlib.py b/debug/testlib.py index d278692..184bc85 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -463,7 +463,7 @@ class Gdb(object): self.select_child(child) self.command(command) - def c(self, wait=True, async=False): + def c(self, wait=True, async=False, checkOutput=True): """ Dumb c command. In RTOS mode, gdb will resume all harts. @@ -477,7 +477,9 @@ class Gdb(object): ops = 10 if wait: output = self.command("c%s" % async, ops=ops) - assert "Continuing" in output + if checkOutput: + assert "Continuing" in output + assert "Could not insert hardware" not in output return output else: self.active_child.sendline("c%s" % async) @@ -579,7 +581,9 @@ class Gdb(object): output = self.command("b %s" % location, ops=5) assert "not defined" not in output assert "Breakpoint" in output - return output + m = re.search(r"Breakpoint (\d+),? ", output) + assert m, output + return int(m.group(1)) def hbreak(self, location): output = self.command("hbreak %s" % location, ops=5) @@ -900,6 +904,7 @@ class GdbTest(BaseTest): if not self.gdb: return self.gdb.interrupt() + self.gdb.command("info breakpoints") self.gdb.command("disassemble", ops=20) self.gdb.command("info registers all", ops=100) self.gdb.command("flush regs") |