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2023-02-02Fix EtriggerTest on multi-hart targets.Tim Newsome1-0/+1
2023-01-06debug: Add Itrigger test.Tim Newsome1-0/+26
2023-01-06debug: Tweak interrupt.c, so a test can run to exit()Tim Newsome1-1/+4
2022-12-29debug: Add etrigger test.Tim Newsome2-1/+20
2022-12-14debug: Add CeaseRunTestTim Newsome1-0/+23
2022-12-14debug: Add CeaseStepiTest.Tim Newsome2-3/+37
2022-12-14debug: Create CeaseMultiTest. (#436)Tim Newsome2-2/+55
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome3-11/+4
2022-12-08Fix regression in VcsSim introduced by #334 (#440)Jerry Zhao1-0/+1
2022-12-01debug: Disassemble memory when a failure happens. (#432)Tim Newsome1-1/+1
2022-12-01`flush regs` -> `maintenance flush register-cache` (#431)Tim Newsome1-1/+1
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome3-2/+23
2022-12-01Share exit() among more tests. (#433)Tim Newsome3-16/+9
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome2-4/+7
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome2-17/+19
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome2-3/+4
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome4-3/+3
2022-10-20Merge pull request #421 from riscv-software-src/pylintTim Newsome1-1/+2
2022-10-12Fix long line to make pylint happy.Tim Newsome1-1/+2
2022-10-12Get coverage of progbuf FPR accesses.Tim Newsome3-2/+9
2022-10-07debug: Add --debug_server arg to open gdb on OpenOCDTim Newsome2-3/+14
2022-10-06Merge pull request #414 from YenHaoChen/pr-timestampTim Newsome1-2/+2
2022-10-05Update testlib.py; remove ANSI escape sequencesYenHaoChen1-1/+2
2022-10-05update gdbserver.py; release tolerance value of MemorySampleTest()YenHaoChen1-2/+2
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
2022-07-22Fix string formatting in testlib.assertTrue()Tim Newsome1-1/+1
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
2022-07-01Complete this pass of pylint changes. (#401)Tim Newsome2-149/+151
2022-06-23Another pylint upgrade. (#398)Tim Newsome3-173/+191
2022-06-08Test semihosting_fileioTim Newsome2-4/+27
2022-05-31Address pylint warnings. (#385)Tim Newsome8-15/+16
2022-05-31Fix GdbTest.disable_pmp failing on systems which support NAPOT but not TOR re...Luke Wren1-2/+8
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
2022-04-25Add EbreakTest. (#380)Tim Newsome2-0/+62
2022-04-07Make download test data const. (#378)Tim Newsome1-2/+2
2022-03-03With new OpenOCD, gdb prints thread info differently (#373)Tim Newsome1-1/+2
2022-03-03Add assert to MemorySampleTest. (#370)Tim Newsome1-0/+1
2022-02-09Debug test to check that stepping doesn't inappropriately switch to Thread 1 ...Greg Savin1-0/+21
2022-01-06Add gdb.interact() for debug tests. (#367)Tim Newsome1-0/+18
2021-11-29Fix TranslateTests. (#365)Tim Newsome2-5/+7
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
2021-11-12Create DisconnectTest. (#364)Tim Newsome2-32/+53
2021-11-12Add timing output to DebugTurboStep. (#362)Tim Newsome1-1/+5
2021-10-05Remove slen. (#360)Tim Newsome4-22/+16
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
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