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| author | Luke Wren <wren6991@gmail.com> | 2021-07-19 22:58:15 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-19 14:58:15 -0700 |
| commit | eeacd5507db7a0f50ca8c4f27aff220fcbb60bdf (patch) | |
| tree | b0736db8b4a4843c3f728124d9256fc18355db87 /debug | |
| parent | 5ce1c35621b19b62fc02b74c27995fb7be74a11c (diff) | |
| download | riscv-tests-eeacd5507db7a0f50ca8c4f27aff220fcbb60bdf.zip riscv-tests-eeacd5507db7a0f50ca8c4f27aff220fcbb60bdf.tar.gz riscv-tests-eeacd5507db7a0f50ca8c4f27aff220fcbb60bdf.tar.bz2 | |
Debug tests: catch write to nonexistent trigger registers in entry.S (#348)
Diffstat (limited to 'debug')
| -rwxr-xr-x | debug/programs/entry.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 3796b3b..091efa4 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -71,6 +71,9 @@ handle_reset: addi t0, t0, -1 bnez t0, 1b + # Catch trap in case trigger module is not implemented + la t2, 2f + csrrw t2, mtvec, t2 # Clear all hardware triggers li t0, ~0 1: @@ -79,6 +82,10 @@ handle_reset: csrw CSR_TDATA1, zero csrr t1, CSR_TSELECT beq t0, t1, 1b +.p2align 2 +2: + # Restore mtvec + csrw mtvec, t2 #ifdef MULTICORE csrr t0, CSR_MHARTID |