| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-02-14 | Add tests for vector register access (#244) | Tim Newsome | 1 | -3/+5 |
| 2019-12-18 | Hardcode misa values for all spike targets. (#227) | Tim Newsome | 1 | -1/+4 |
| 2019-05-16 | Cover with/without halt groups. (#191) | Tim Newsome | 1 | -1/+1 |
| 2019-04-08 | Test lack of abstract CSR access. (#187) | Tim Newsome | 1 | -1/+2 |
| 2018-12-31 | Add testing of run-test/idle cases. | Tim Newsome | 1 | -1/+1 |
| 2018-08-29 | Add test case for `riscv expose_custom`. | Tim Newsome | 1 | -0/+1 |
| 2017-12-27 | Test FPRs that aren't XLEN in size. | Tim Newsome | 1 | -1/+2 |
| 2017-09-29 | Fix tests to work in multi-gdb mode. | Tim Newsome | 1 | -1/+1 |
| 2017-09-19 | Allow multiple reset vectors. | Tim Newsome | 1 | -1/+1 |
| 2017-09-01 | Use 32-bit link script for 32-bit target. | Tim Newsome | 1 | -1/+1 |
| 2017-08-28 | Increase remotetimeout for spike targets. | Tim Newsome | 1 | -0/+1 |
| 2017-08-28 | Make the debug tests aware of multicore. | Tim Newsome | 1 | -1/+6 |
| 2017-06-26 | Move target definition into individual files. | Tim Newsome | 1 | -0/+12 |
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index : riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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