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2023-01-19Fix ma_fetch test for writable misa.C (#449)Jerry Zhao1-3/+3
2023-01-19Pass --misaligned flag to Spike to run ISA tests (#445)Andrew Waterman1-2/+2
...because the ma_data test requires this feature. Don't merge until https://github.com/riscv-software-src/riscv-isa-sim/pull/1206 is merged.
2023-01-06Merge pull request #446 from riscv-software-src/itriggerTim Newsome2-1/+30
debug: Add Itrigger test.
2023-01-06debug: Add Itrigger test.Tim Newsome1-0/+26
2023-01-06debug: Tweak interrupt.c, so a test can run to exit()Tim Newsome1-1/+4
2023-01-06Merge pull request #447 from riscv-software-src/etriggerTim Newsome2-1/+20
debug: Add etrigger test.
2022-12-29Merge branch 'jerryz123-fix-ma_fetch'Andrew Waterman1-9/+31
2022-12-29debug: Add etrigger test.Tim Newsome2-1/+20
2022-12-28Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32Jerry Zhao1-9/+31
2022-12-28Fix clean in isa/ with non-default compiler (#443)Alex Shpilkin1-1/+1
The list of active tests in isa/ depends, via the COMPILER_SUPPORTS_* macros, on running the RISC-V compiler, so pass the necessary options when invoking make clean there.
2022-12-27Merge pull request #442 from riscv-software-src/ceasetestTim Newsome2-3/+60
Add CeaseStepiTest and CeaseRunTest
2022-12-14debug: Add CeaseRunTestTim Newsome1-0/+23
Test that we work correctly when the hart we're debugging ceases to respond while it's running.
2022-12-14debug: Add CeaseStepiTest.Tim Newsome2-3/+37
Test that we work correctly when the hart we're debugging ceases to respond during stepi. Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete. Parse "could not read registers" error from gdb
2022-12-14debug: Create CeaseMultiTest. (#436)Tim Newsome2-2/+55
Confirm basic debug still works when other harts have been parked using a `cease` instruction. Check that the unavailable harts are inaccessible from gdb. Add Gdb.expect() Parse "unknown thread" error from gdb.
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome3-11/+4
Also make the semi-hosting test program return 10. That's more fragile than returning 0, so makes for a better test.
2022-12-08Fix regression in VcsSim introduced by #334 (#440)Jerry Zhao1-0/+1
2022-12-07zicntr: separate cycle/instret accessibility test (#439)Chih-Min Chao5-16/+69
It is allowed that M-mode only implementation could skip cycle/instret if the Zicntr is not included. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-12-01debug: Disassemble memory when a failure happens. (#432)Tim Newsome1-1/+1
This gives you less noise in the log, and more chance of figuring out what code was actually executed.
2022-12-01`flush regs` -> `maintenance flush register-cache` (#431)Tim Newsome1-1/+1
`flush regs` is being deprecated.
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome3-2/+23
`cease` is not a standard RISC-V extension, but is (was?) implemented in Rocket, and also exists in some SiFive cores. It's useful to test OpenOCD behavior when a hart becomes unavailable. See also https://github.com/chipsalliance/rocket-chip/issues/1868
2022-12-01Share exit() among more tests. (#433)Tim Newsome3-16/+9
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome2-4/+7
Also change the test itself to require less RAM than it did previously. (It had required more than 32KB.)
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome2-17/+19
It would fail intermittently. We can't guarantee all harts resume simultaneously. When we let multiple harts run to a breakpoint at the end of the same loop, one is likely to get there first, and the second won't make it. To avoid this problem, run for a short amount of time instead of to a breakpoint.
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
Before it might fail incorrectly, because main was close to trap_entry.
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
* Specify trigger type=2 in trigger.S Previous tests implicitly assume triggers only support type=2. However, a trigger may support multiple types, i.e., type=15. This commit explicitly specifies type=2 in trigger.S to support type 15. * Update debug/programs/trigger.S Co-authored-by: Tim Newsome <tim@sifive.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> Co-authored-by: Tim Newsome <tim@sifive.com>
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome2-3/+4
Between October 13 and October 19, something happened that makes the multi-spike tests 4 times slower. Rolling back spike, OpenOCD, or riscv-tests doesn't affect this. Presumably it's due to a kernel or python change in my Ubuntu system. I don't have time to look at this right now, so just increase the timeouts. :-( If I had to guess, there could be a bug in rbb_daisychain.py that wastes a lot of time.
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome4-3/+3
https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART at the address we were using in our 32-bit debug tests.
2022-10-20Merge pull request #421 from riscv-software-src/pylintTim Newsome1-1/+2
Fix long line to make pylint happy.
2022-10-20Merge pull request #420 from riscv-software-src/test_fpr_progbufTim Newsome3-2/+9
Get coverage of progbuf FPR accesses.
2022-10-12Fix long line to make pylint happy.Tim Newsome1-1/+2
2022-10-12Get coverage of progbuf FPR accesses.Tim Newsome3-2/+9
Using the new spike support merged in https://github.com/riscv-software-src/riscv-isa-sim/pull/1109
2022-10-10Merge pull request #417 from riscv-software-src/debug_serverTim Newsome2-3/+14
debug: Add --debug_server arg to open gdb on OpenOCD
2022-10-07debug: Add --debug_server arg to open gdb on OpenOCDTim Newsome2-3/+14
Not as useful as I'd like because we don't connect until after examine() has completed, and the test is likely to time out while debugging. But good to have, and maybe I'll expand on it one day.
2022-10-06Merge pull request #414 from YenHaoChen/pr-timestampTim Newsome1-2/+2
update gdbserver.py; tolerance value of MemorySampleTest()
2022-10-05Update testlib.py; remove ANSI escape sequencesYenHaoChen1-1/+2
The control sequences (^[[?2004h and ^[[?2004l) occur after the gdb.command, which results in Exception fault. This commit removes the control sequences and strips out the blank lines (^M).
2022-10-05update gdbserver.py; release tolerance value of MemorySampleTest()YenHaoChen1-2/+2
2022-09-27rv64ui test misaligned load/store data (#410)John Ingalls2-0/+388
2022-09-27zicboz: comment # (#412)John Ingalls1-1/+1
2022-09-26zicbo test zero (#411)John Ingalls3-2/+49
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
These can change at any time and that is OK.
2022-07-22Fix string formatting in testlib.assertTrue()Tim Newsome1-1/+1
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
I don't have time to fix the bug right now, and nobody has run into the bug yet in any case.
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
Turn semihosting_fileio on for every hart. This test still fails if it ends up running on hart 1 instead of 0, but at least it's closer to passing. Feels like the remaining problem is in OpenOCD.
2022-07-01Complete this pass of pylint changes. (#401)Tim Newsome2-149/+151
2022-06-23Another pylint upgrade. (#398)Tim Newsome3-173/+191
* Another pylint upgrade. Lots of format string changes, which are more readable. More files to come... * Satisfy pylint for two more files.
2022-06-21Update information about Makefile fragments (#399)Mehmet Oguz Derin1-4/+2
The source of benchmarks' Makefile does not use fragments anymore. This commit removes the mention of them from the readme. Signed-off-by: Mehmet Oguz Derin <mehmetoguzderin@mehmetoguzderin.com>
2022-06-09Test misaligned stores. (#397)Tim Newsome8-0/+158
Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support).
2022-06-08Merge pull request #395 from riscv-software-src/misaligned_storeAndrew Waterman10-6/+164
Test misaligned stores
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