diff options
-rw-r--r-- | isa/rv64si/ma_fetch.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index 22eadc9..255ad48 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -120,10 +120,10 @@ RVTEST_CODE_BEGIN bnez t2, pass # Skip if clearing misa.C does not set IALIGN=32 - csrr t0, mepc + csrr t0, mtvec la t1, 1f addi t1, t1, 2 - csrw mepc, t1 + csrw mtvec, t1 j 1f .option rvc @@ -132,7 +132,7 @@ RVTEST_CODE_BEGIN j pass .option norvc 2: - csrw mepc, t0 + csrw mtvec, t0 csrsi misa, 1 << ('c' - 'a') # IALIGN=32 cannot be set if doing so would cause a misaligned instruction |